Semiconductor device, manufacturing method thereof, and display device

ABSTRACT

A multi-gate structure is used and a width (d 1 ) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d 2 ) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device which has acircuit composed of a thin film transistor (hereinafter referred to as aTFT) and a manufacturing method thereof. The present invention relatesto, for example, an electro-optical device represented by a liquidcrystal display panel and electronic equipment in which such anelectro-optical device is mounted as a part.

Note that in this specification, a semiconductor device indicates ageneral device which functions by utilizing semiconductorcharacteristics, and an electro-optical device, a semiconductor circuit,and an electronic device are each a semiconductor device.

2. Description of the Related Art

In recent years, the development of a semiconductor device, which has alarge area integrated circuit manufactured from a thin film transistor(TFT) using a semiconductor thin film (about several nm to severalhundred nm in thickness) formed on a substrate with an insulatingsurface, has been progressed. An active matrix liquid crystal displaydevice, an EL display device, and a contact type image sensor have beenknown as typical examples thereof. In particular, since a TFT using acrystalline silicon film (typically, a polysilicon film) as an activelayer (hereinafter referred to as a polysilicon TFT) has high fieldeffect mobility, it is also possible to form various functionalcircuits.

For example, in the case of the active matrix liquid crystal displaydevice, a pixel circuit for displaying an image in each functional blockand a driver circuit for controlling the pixel circuit, which iscomposed of a shift register circuit, a level shifter circuit, a buffercircuit, a sampling circuit, and the like using CMOS circuits asfundamental circuits, are formed on a single substrate.

In the case of the pixel circuit of the active matrix liquid crystaldisplay device, TFTs (pixel TFTs) are arranged in several tens toseveral millions of pixels and a pixel electrode is provided in each ofthe pixel TFTs. An opposing electrode is provided at an opposingsubstrate side sandwiching liquid crystal, and a kind of capacitor usingthe liquid crystal as a dielectric is formed. Thus, voltage applied toeach of the pixels is controlled by a switching function of the TFT tocontrol a charge to the capacitor and drive the liquid crystal, theamount of transmitting light is controlled to display an image.

The use of such an active matrix liquid crystal display device has beendiversified and the demand for high definition, high aperture ratio, andhigh reliability has been increased as a screen size becomes larger inarea. Also, simultaneously, the demand for an improvement ofproductivity and a reduction in a cost has been increased.

An advantage of the active matrix display device is that an integratedcircuit such as a shift register, a latch, or a buffer, which iscomposed of TFTs, can be formed as a driver circuit for transmittingsignals to a pixel portion on the same substrate. Thus, the number ofcontact points with external circuits can be extremely reduced toimprove the reliability of the display device.

Also, the pixel TFT is an n-channel TFT and used as a switching elementfor applying voltage to liquid crystal for driving. Since the liquidcrystal is driven by an alternating current, a method called frameinverting drive is employed in many cases. In this method, in order todecrease the power consumption, it is important to sufficiently reducean off current value (drain current flowing in placing the TFT in an offoperation state) as a characteristic required for the pixel TFT. Inaddition, a characteristic such as a sufficient small parasiticcapacitance between a gate and a drain is required. Since a pixelcapacitance is small to cause an insufficient retaining operation, anauxiliary capacitor is provided in a pixel to implement such anoperation and to prevent the influence of the parasitic capacitor.

A low concentration drain (LDD: lightly doped drain) structure has beenknown as a structure of a TFT for reducing an off current value.According to this structure, a region to which an impurity element isadded at a low concentration is provided between a channel formingregion and a source region or a drain region which is formed by addingan impurity element at a high concentration, and this region is called aLDD region.

Also, a multi-gate structure such as a double gate structure or a triplegate structure, which has a plurality of channel forming regions, hasbeen known as a structure of a TFT for reducing a variation in an offcurrent value. As shown in FIGS. 27A and 27B, when two TFTs are simplyconnected with each other to obtain a double gate structure, a totalsize of the TFTs for one pixel becomes large and this causes a reductionin an aperture ratio.

In a pixel for an active matrix driving system, a pixel electrode forapplying voltage to liquid crystal is provided and a scan line (gateline) connected with a gate electrode and a data line connected with asource or a drain are intersected. Two types, an additional capacitortype in which the pixel electrode and the fore stage scan line (gateline) are overlapped with each other and a storage capacitor type inwhich a dedicated capacitor line is provided, have been known asauxiliary capacitors. In either of the two types, the allowable sizes ofa TFT and an auxiliary capacitor for one pixel are necessarily reducedwith an improved definition of an image. Thus, in order to obtain a highaperture ratio for respective pixels in a specific pixel size, it isessential that elements required for a structure of the pixels isefficiently laid out.

Also, with respect to the liquid crystal display device, two types, adirect view type for directly viewing an image displayed in a pixelportion and a projection type for displaying an image on a screen usingan optical system, are being developed. Both types are selectively usedbased on a screen size, and the direct view type is used for a size upto about 30 inches and the projection type is used for the size orlarger.

Also, in the case of all liquid crystal display devices, particularly, aliquid crystal display device for a projector, a variation in acharacteristic of a TFT located in each pixel is caused by a photo leakcurrent produced by incidence light into a semiconductor layer throughvarious paths. Thus, a deterioration of an image quality (reduction in acontrast, a flicker, a cross talk, or the like) becomes a problem.

SUMMARY OF THE INVENTION

There is a problem that compatibility of an increase in an apertureratio and a reduction in a photo leak current or compatibility of anincrease in the aperture ratio and a reduction in an off current valueis difficult in the above-mentioned conventional pixel structure or TFTstructure.

Such a requirement becomes a large problem in the case where a pitch ofrespective display pixels is reduced with an increased definition(increasing the number of pixels) of the liquid crystal display deviceand the miniaturized liquid crystal display device.

Also, since a TFT with a multi-gate structure has a small on currentvalue, which becomes a failure in the case where high speed drive isperformed in the liquid crystal display device.

An object of the present invention is to provide a TFT structure whichis resistant to a deterioration of image quality by incidence light intoa semiconductor layer and which occupies a reduced area in one pixeltogether, in addition to providing a TFT structure with a small offcurrent value and a large on current value.

Also, in the case of a transmission type active matrix liquid crystaldisplay device, a light shielding layer is a necessary element. Thesemiconductor layer has a photoconductive effect in which a resistancevalue is changed by light irradiation, and an off current is increasedby irradiating light from a light source thereto. In particular, in thecase of a projection type display device, it becomes a problem that aportion of light transmitting the liquid crystal display device isreflected from the boundary between a substrate and an air layer orreflected from an optical system and then returned in an oppositedirection into a TFT.

In the case of the projection type using a metal halide lamp or the likeas a light source, a design of the light shielding layer is importantsince 100 millions lux to 2000 millions lux of light is irradiated tothe liquid crystal display device. On the other hand, it is requiredthat incidence light into the TFT is suppressed to about 100 lux toreduce an off current. Generally, although the light shielding layer isformed in the upper layer portion or the lower layer portion of thesemiconductor layer in the TFT, about 0.1% to 1% of incidence light(light from a light source) is incident thereinto as diffraction light.

With respect to the semiconductor layer, conductivity is increased bythe photoconductive effect to increase an off current of the TFT. Thus,image display is affected by a reduction in a contrast, an occurrence ofa cross talk, or the like. However, when light shielding property haspriority to increase an area of the light shielding layer in order toblock such light, an aperture ratio is naturally reduced.

In order to realize a high aperture ratio in a specific pixel size, itis essential that elements required for a structure of a pixel portionare efficiently laid out. An object of the present invention is toprovide an active matrix display device which has a pixel structure inwhich a high aperture ratio is realized by suitably arranging a pixelelectrode, a scan line (gate line), and a data line, which are formed ina pixel portion.

Also, as means for forming a crystalline silicon film on an insulatingsurface, a method of crystallizing an amorphous silicon film by laserannealing or thermal treatment using an electric heat furnace is used inaddition to a method of directly forming a crystalline silicon film by alow pressure CVD method. Even when either of these methods is applied, afield effect mobility value of only about 100 cm/Vsec to 200 cm²/Vseccan be obtained in an n-channel TFT and a field effect mobility value ofonly about 50 cm²/Vsec to 100 cm²/Vsec can be obtained in a p-channelTFT. In addition, since a threshold voltage is 3 V in the n-channel TFTand a subthreshold coefficient (S value) is 300 mV/dec, a drive voltagebecomes 14 V. Thus, reductions in a power source voltage and powerconsumption are challenges.

In order to realize a low voltage and low power consumption, it isnecessary to increase a size of crystal grain in the crystalline siliconfilm, improve the mobility, and reduce the S value. In addition, it isrequired that a variation in the threshold voltage is suppressed.

With respect to a technique for increasing the size of crystal grainsand an application thereof to the TFT, there is a report example in“Ultra-high Performance Poly-Si TFTs on a Glass by a Stable Scanning CWLaser Lateral Crystallization”, A. Hara, F. Takeuchi, M. Takei, K.Yoshino, K. Suga and N. Sasaki, AMLCD, '01, Tech. Dig., 2001, pp.227-230. According to the report example, it is described that a TFT isprototyped from a polycrystalline silicon film crystallized using thesecond harmonic of a solid continuous oscillating laser (YVO₄) by diodeexcitation and the improvement of field effect mobility is reported as aresult.

However, even when a large size in the crystalline silicon film can berealized, in the case of a structure in which the light shielding filmand the semiconductor film are overlapped with each other, the lightshielding film is altered in irradiation of continuous oscillating laserlight and laser light reflected from the light shielding film formed inthe lower layer side of the semiconductor film is diffused to inhibituniform crystallization. Thus, it becomes a problem that a distortion isaccumulated and a threshold voltage is varied.

Also, when an internal stress from the light shielding film and aninsulating film, which are formed in the lower layer side of thesemiconductor film, is changed in the irradiation of continuousoscillating laser light, a problem in that the threshold voltage isvaried is caused.

In addition, the present invention has been made in view of the aboveproblems and an object thereof is also to reduce driving voltages ofvarious integrated circuits composed of TFTs to realize low powerconsumption.

According to the present invention, a multi-gate structure such as adouble gate structure or a triple gate structure which has a pluralityof channel forming regions is used for a pixel TFT and an intervalbetween adjacent gate electrodes in one pixel TFT is made to be shorterthan a width of a low concentration impurity region (LDD region). In onepixel TFT with a multi-gate structure, the low concentration impurityregion is provided between a source region and a channel forming regionwhich is located in the nearest position to the source region, andbetween a drain region and a channel forming region which is located inthe nearest position to the drain region, in two locations in total.Note that, since a pixel using liquid crystal is generally driven by analternating current, the source region and the drain region in the pixelTFT are alternately changed. Thus, a width of a low concentrationimpurity region provided between one channel forming region and thesource region is equal to that of a low concentration impurity regionprovided between the other channel forming region and the drain region.

Also, only a high concentration impurity region containing an impurityelement at a concentration which is approximately the same as or higherthan the source region or the drain region, is formed as a regionsandwiched by two adjacent channel forming region in one TFT. Thus,while the resistance of the entire semiconductor layer of a TFT which isin an on state is reduced, light sensitivity is reduced in the case ofincidence light into the TFT for some reason.

In other word, according to the present invention, a width of the highconcentration impurity region sandwiched by two adjacent channel formingregions in a channel length direction is made to be shorter than that ofthe low concentration impurity region in the channel length direction.Thus, an occupying area of a TFT in one pixel is reduced to improve anaperture ratio of the pixel. In addition, according to the presentinvention, the plurality of channel forming regions are provided. Thus,even if a failure such as a current leakage is caused in one channelforming region, the other channel forming region normally functions toreduce an abnormal value of an off current to suppress the variation.Further, even if light shielding property to the pixel TFT isdeteriorated for some reason and light is incident into the TFT, thelight sensitivity in an off current value is reduced to suppress adisplay failure.

According to a structure (1) disclosed in this specification, there isprovided a semiconductor device including a TFT that has a semiconductorlayer formed on an insulating surface, an insulating film formed on thesemiconductor layer, and a plurality of gate electrodes formed on theinsulating film, characterized in that the semiconductor layer has: aplurality of channel forming regions overlapped with the gate electrodesthrough the insulating film interposed therebetween; a source region; adrain region; and a low concentration impurity region located betweenone of the channel forming regions and one of the source region and thedrain region, and that an interval between two adjacent gate electrodesof the plurality of gate electrodes is shorter than a width of the lowconcentration impurity region.

Also, according to another structure (2) of the present invention, thereis provided a semiconductor device including a TFT that has asemiconductor layer formed on an insulating surface, an insulating filmformed on the semiconductor layer, and a plurality of gate electrodesformed on the insulating film, characterized in that the semiconductorlayer has: a plurality of channel forming regions overlapped with thegate electrodes through the insulating film interposed therebetween; asource region; a drain region; a high concentration impurity regionlocated adjacent to two of the plurality of channel forming regions; anda low concentration impurity region located between one of the channelforming regions and one of the source region and the drain region, andthat an interval between two adjacent gate electrodes of the pluralityof gate electrodes is shorter than a width of the low concentrationimpurity region.

With respect to the above structure (2), when the high concentrationimpurity region and the source region or the drain region are formed inthe same step, the high concentration impurity region have the sameimpurity concentration as the source region or the drain region.

Also, with respect to the above structure (2), when the highconcentration impurity region is formed in a separate step from thesource region or the drain region, the high concentration impurityregion can have a higher impurity concentration than the source regionor the drain region. Thus, when the concentration of the highconcentration impurity region is higher than that of another region, theresistance of the entire semiconductor layer of a TFT which is in an onstate is reduced to increase an on current. In addition, a carrier lifetime due to photoexcitation produced in the high concentration impurityregion can be shortened to reduce light sensitivity.

Also, with respect to the above structure (2), when the highconcentration impurity region is formed in a separate step from thesource region or the drain region, the high concentration impurityregion have an impurity concentration which is higher than the lowconcentration impurity region and lower than the source region or thedrain region.

Also, with respect to the above structure (2), the width of the highconcentration impurity region is equal to an interval between adjacentgate electrodes.

Also, with respect to the above structure (1) or the above structure(2), an interval between two adjacent channel forming regions of theplurality of channel forming regions is equal to that between twoadjacent gate electrodes.

Also, when the present invention is applied to the TFT with the doublegate structure, the following TFT structure is used. That is, a lowconcentration impurity region (LDD region) is provided between onechannel forming region and the drain region, a low concentrationimpurity region (LDD region) is provided between the other channelforming region and the source region, and a high concentration impurityregion is provided between the two channel forming regions. Thus, thewidth of the high concentration impurity region in the channel lengthdirection is made to be shorter than that of the low concentrationimpurity region in the channel length region.

Also, according to another structure (3) of the present invention, thereis provided a semiconductor device including a TFT that has asemiconductor layer formed on an insulating surface, an insulating filmformed on the semiconductor layer, and a first gate electrode and asecond gate electrode which are formed on the insulating film,characterized in that the semiconductor layer has: a first channelforming region overlapped with the first gate electrode through theinsulating film interposed therebetween, a second channel forming regionoverlapped with the second gate electrode through the insulating filminterposed therebetween; a high concentration impurity region locatedadjacent to both the first channel forming region and the second channelforming region; a first low concentration impurity region located incontact with the first channel forming region; a drain region located incontact with the first low concentration impurity region; a second lowconcentration impurity region located in contact with the second channelforming region; and a source region located in contact with the secondlow concentration impurity region, and that an interval between thefirst gate electrode and the second gate electrode is shorter than awidth of the first low concentration impurity region.

With respect to the above structure (3), when the high concentrationimpurity region and the source region or the drain region are formed inthe same step, the high concentration impurity region can have at thesame impurity concentration as the source region or the drain region.

Also, with respect to the above structure (3), when the highconcentration impurity region is formed in a separate step from thesource region or the drain region, the high concentration impurityregion can have a higher impurity concentration than the source regionor the drain region. Thus, when the concentration of the highconcentration impurity region is higher than that of another region, theresistance of the entire semiconductor layer of a TFT which is in an onstate is reduced to increase an on current. In addition, a carrier lifetime due to photoexcitation produced in the high concentration impurityregion can be shortened to reduce light sensitivity.

Also, with respect to the above structure (3), when the highconcentration impurity region is formed in a separate step from thesource region or the drain region, the high concentration impurityregion can have an impurity concentration which is higher than the lowconcentration impurity region and lower than the source region or thedrain region.

Also, with respect to the above structure (3), the width of the highconcentration impurity region is equal to or shorter than that of thefirst low concentration impurity region.

Also, with respect to the above structure (3), the width of the highconcentration impurity region is equal to or shorter than that of thesecond low concentration impurity region.

Also, according to the present invention, a TFT structure in which thehigh concentration impurity region is provided between the two channelforming regions is used. Thus, the width of the high concentrationimpurity region in the channel length direction may be equal to that ofthe low concentration impurity region in the channel length region.

Also, according to another structure (4) or the present invention, thereis provided a semiconductor device including a TFT that has asemiconductor layer formed on an insulating surface, an insulating filmformed on the semiconductor layer, and a plurality of gate electrodesformed on the insulating film, characterized in that the semiconductorlayer has; a plurality of channel forming regions overlapped with thegate electrodes through the insulating film interposed therebetween; asource region; a drain region; a high concentration impurity regionlocated adjacent to two of the plurality of channel forming regions; anda low concentration impurity region located between one of the channelforming regions and one of the source region and the drain region, andthat an interval between two adjacent gate electrodes of the pluralityof gate electrodes is equal to a width of the low concentration impurityregion.

With respect to the above structure (4), when the high concentrationimpurity region and the source region or the drain region are formed inthe same step, the high concentration impurity region can have the sameimpurity concentration as the source region or the drain region.

Also, with respect to the above structure (4), when the highconcentration impurity region is formed in a separate step from thesource region or drain region, the high concentration impurity regioncan have a higher impurity concentration than the source region or thedrain region. Thus, when the concentration of the high concentrationimpurity region is higher than that of another region, the resistance ofthe entire semiconductor layer of a TFT which is in an on state isreduced to increase an on current. In addition, a carrier life time dueto photoexcitation produced in the high concentration impurity regioncan be shortened to reduce light sensitivity.

Also, with respect to the above structure (4), when the highconcentration impurity region is formed in a separate step from thesource region or the drain region, the high concentration impurityregion can have an impurity concentration which is higher than the lowconcentration impurity region and lower than the source region or thedrain region.

Also, with respect to the above structures (1) to (4), the TFT is ann-channel TFT or a p-channel TFT.

Also, with respect to the above structures (1) to (4), a semiconductordevice is typically a liquid crystal display device or a light emittingdevice having an EL element, which has a pixel electrode electricallyconnected to the source region or the drain region.

Also, with respect to a display device of the present invention, in asemiconductor device (typically, a liquid crystal display device) inwhich a pixel electrode, a thin film transistor, and a capacitor elementare provided on a substrate, one electrode of the capacitor element isconnected with one of a source and a drain of the thin film transistor,and the electrode is extended over a gate electrode of the thin filmtransistor.

Also, according to another structure, there is provided a semiconductordevice in which a pixel electrode, a thin film transistor, and acapacitor element are provided on a substrate, one electrode of thecapacitor element is connected with one of a source and a drain of thethin film transistor, and the electrode is extended over a gateelectrode of the thin film transistor as a light shielding layer andoverlapped with another light shielding layer provided in the upperlayer of the gate electrode.

Also, according to another structure, there is provided a semiconductordevice in which a pixel electrode, a thin film transistor, and acapacitor element are provided on a substrate, one electrode of thecapacitor element, which is formed on an insulating layer, is connectedwith one of a source and a drain of the thin film transistor, theinsulating layer covers a gate electrode of the thin film transistor,and the electrode is extended over the gate electrode of the thin filmtransistor and overlapped with another light shielding layer provided inthe upper layer of the gate electrode.

Also, according to another structure, there is provided a semiconductordevice including: a substrate; a semiconductor layer formed over thesubstrate: a first light shielding layer formed between the substrateand the semiconductor layer; a gate electrode formed over thesemiconductor layer; a pixel electrode formed in an upper layer of thegate electrode; a third light shielding layer formed between the gateelectrode and the pixel electrode; and a second light shielding layerformed between the gate electrode and the third light shielding layer,wherein the gate electrode is overlapped with the first, the second, andthe third light shielding layers.

Also, according to another structure, there is provided a semiconductordevice in which a pixel electrode, a thin film transistor, and acapacitor element are provided on a substrate, the semiconductor devicecomprising: a first light shielding layer formed over the substrate; afirst insulating layer formed on the first light shielding layer; asemiconductor layer formed on the first insulating layer, a secondinsulating layer formed on the semiconductor layer; a gate electrode anda capacitor wiring which are formed on the second insulating layer; athird insulating layer formed on the gate electrode and the capacitorwiring; a second light shielding layer formed on the third insulatinglayer; a fourth insulating layer formed on the second light shieldinglayer; source and drain wirings formed on the fourth insulating layer; afifth insulating layer formed on the source and drain wiring; a thirdlight shielding layer formed on the fifth insulating layer; a sixthinsulating layer formed on the third light shielding layer; and a pixelelectrode formed on the sixth insulating layer, wherein the capacitorelement is formed by the semiconductor layer, the second insulatinglayer, the capacitor wiring, the third insulating layer, and the secondlight shielding layer, and the second light shielding layer is extendedover the gate electrode.

According to the above structure, when the light shielding layer isextended over the gate electrode, incidence of diffraction light intothe semiconductor layer and an increase in an off current of the TFT bythe diffraction light can be prevented. In addition, when elementsrequired for the structure of the pixel portion are efficientlyarranged, a high aperture ratio can be realized in a specific pixelsize.

Also, in order to reduce drive voltages of various integrated circuitscomposed of TFTs to realize low power consumption, a structure of thepresent invention is characterized by including a second crystallinesemiconductor film formed in contact with a first crystallinesemiconductor film over an insulating substrate, a first light shieldingfilm formed between the insulating substrate and the first crystallinesemiconductor film, a gate electrode formed over the second crystallinesemiconductor film, a pixel electrode formed over the gate electrode, athird light shielding layer formed between the gate electrode and thepixel electrode, and a second light shielding layer formed between thegate electrode and the third light shielding layer, in which an averagecrystal grain size in the second crystalline semiconductor film islarger than that in the first crystalline semiconductor film.

Also, according to the present invention, there is provided a method ofmanufacturing a semiconductor device including the steps of: forming afirst conductive layer which has a light shielding property on aninsulating surface; forming a first insulating layer covering the firstconductive layer; forming a first amorphous semiconductor film on thefirst insulating layer; crystallizing the first amorphous semiconductorfilm by thermal treatment without melting to form a first crystallinesemiconductor film; forming a second amorphous semiconductor film on thefirst crystalline semiconductor film; and crystallizing the secondamorphous semiconductor film after melting a portion or a whole thereofby irradiation of laser light.

In the above structure of the present invention, a solid laseroscillating device or a gas laser oscillating device is applied as alight source for laser light. One kind of device with continuousoscillation or pulse oscillation selected from the group consisting of aYAG laser oscillating device, a YVO₄ laser oscillating device, a YLFlaser oscillating device, a YAlO₃ laser oscillating device, a glasslaser oscillating device, a ruby laser oscillating device, analexandrite laser oscillating device, and a Ti: sapphire laseroscillating device is applied as the solid laser oscillating device. Itis desirable that laser light is converted into the second harmonic orthe third harmonic by a non-linear optical element. One kind of devicewith continuous oscillation or pulse oscillation selected from the groupconsisting of an excimer laser oscillating device, an Ar laseroscillating device, a Kr laser oscillating device, and a CO₂ laseroscillating device is applied as the gas laser. In addition, a heliumcadmium laser oscillating device, a copper vapor laser oscillatingdevice, and a gold vapor laser oscillating device may be applied as ametallic laser oscillating device.

After the first crystalline semiconductor film is formed, the secondamorphous semiconductor film is formed and crystallized by irradiationof laser light. Thus, the first crystalline semiconductor film functionsto relax an internal stress at laser irradiation from a different kindof film, the base insulating film and the light shielding film. Inaddition, the first crystalline semiconductor film prevents thealternation of the light shielding film due to the irradiation of laserlight, and diffuse reflection of the laser light reflected from thelight shielding film formed under the first crystalline semiconductorfilm. Therefore, the accumulation of a distortion is relaxed and avariation in a threshold voltage of a TFT can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are a cross sectional view and a top view according tothe present invention (Embodiment Mode 1);

FIGS. 2A and 2B are a cross sectional view and a top view according tothe present invention (Embodiment Mode 2);

FIG. 3 is a graph indicating a probability distribution of an on currentvalue;

FIG. 4 is a graph indicating a probability distribution of an offcurrent value;

FIGS. 5A to 5C show steps of manufacturing an active matrix substrate;

FIGS. 6A to 6C show steps of manufacturing the active matrix substrate;

FIG. 7 shows a step of manufacturing the active matrix substrate;

FIG. 8 is a top view of a pixel;

FIG. 9 shows an appearance of a liquid crystal module;

FIGS. 10A to 10D show steps of manufacturing an active matrix substrate;

FIGS. 11A to 11D show steps of manufacturing the active matrixsubstrate;

FIGS. 12A to 12D show steps of manufacturing the active matrixsubstrate;

FIGS. 13A to 13C show steps of manufacturing the active matrixsubstrate;

FIGS. 14A and 14B show steps of manufacturing the active matrixsubstrate;

FIGS. 15A and 15B show steps of manufacturing the active matrixsubstrate;

FIG. 16 is a cross sectional view according to the present invention(Embodiment 5);

FIG. 17 is a cross sectional view according to the present invention(Embodiment 5):

FIGS. 18A to 18F show examples of electronic devices;

FIGS. 19A to 19D show examples of electronic devices;

FIGS. 20A to 20C show examples of electronic devices;

FIG. 21 is a cross sectional view of a thin film transistor and pixelstructure according to Embodiment Mode 3;

FIGS. 22A and 22B show steps of manufacturing an active matrix substrate(Embodiment 7);

FIGS. 23A and 23B show a result obtained by simulating an electric fieldstrength distribution of an LDD region in a structure of the presentinvention;

FIGS. 24A and 24B show a result obtained by simulating an electric fieldstrength distribution of an LDD region in a conventional structure;

FIG. 25 is a graph indicating static characteristics of a TFT in thestructure of the present invention and the conventional structure;

FIG. 26 is a cross sectional view of a thin film transistor and pixelstructure according to Embodiment Mode 4; and

FIGS. 27A and 27B show a conventional example.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment Mode 1

One example in the case of applying the present invention to a TFT witha double gate structure is shown in FIGS. 1A and 1B and described below.

In FIGS. 1A and 1B, reference numeral 100 denotes a substrate, 101 and102 denote channel forming regions, 103 and 105 denote a source regionand a drain region, 104 denotes a high concentration impurity region,106 and 107 denote low concentration impurity regions (LDD regions), 108denotes a gate insulating film, 109 denotes gate electrodes, 110 denotesan interlayer insulating film, and 111 and 112 denote a source electrodeand a drain electrode. Note that FIG. 1A is a cross sectional view takenalong the dotted line A-A′ of FIG. 1B which is a top view of a TFT.

The present invention is characterized in that only the highconcentration impurity region 104 is formed as a region sandwiched bythe two channel forming regions 101 and 102. An interval d1 between theadjacent gate electrodes 109, that is, a width of the high concentrationimpurity region in a channel length direction is designed to be shorterthan a width d2 of the low concentration impurity regions 106 and 107.Thus, the interval between the two channel forming regions can beshortened and an area occupied by the TFT in one pixel can be reduced.In addition, since the region sandwiched by the two channel formingregions is the high concentration impurity region, light sensitivity inthe case where light is incident into a TFT for some reason is reducedwhile the resistance of the entire semiconductor layer of the TFT whichis in an on state is reduced.

Conventionally, it is necessary to form the LDD regions sandwiching thechannel forming region in both sides thereof and there is a TFTstructure including a double gate structure (disclosed in JP 06-265940A) in which two TFTs are simply connected with each other (hereinaftercalled an A-type) as shown in FIGS. 27A and 27B. In this structure(A-type), an area occupied by the TFT in one pixel is increased. Notethat, according to this TFT structure (A-type), as shown in FIGS. 27Aand 27B, both low concentration impurity regions 16 and 17 and a highconcentration impurity region 14 are formed between two channel formingregions 11 and 12, which is greatly different from the presentinvention. In addition, according to this structure (A-type), aninterval d1 between adjacent gate electrodes 19 becomes longer than awidth d2 of the low concentration impurity regions 16 and 17, that is,d1>d2. According to the TFT structure of the present invention, only thehigh concentration impurity region is formed between the two channelforming regions and an on current value is larger than that in the TFTstructure (A-type). Note that, in FIGS. 27A and 27B, reference numeral10 denotes a substrate, 13 and 15 denote a source region and a drainregion, 18 denotes a gate insulating film, 20 denotes an interlayerinsulating film, and 21 and 22 denote a source electrode and a drainelectrode.

Also, a TFT structure disclosed in JP 04-344618 A and JP 07-263705 A isproposed. According to the TFT structure disclosed in these documents(hereinafter called a B-type), only a low concentration impurity regionis formed between two channel forming regions, which is greatlydifferent from the present invention. According to the TFT structure ofthe present invention, only the high concentration impurity region isformed between the two channel forming regions and an on current valueis larger than that in the TFT structure (B-type). In addition, d1>d2 inthe TFT structure (B-type).

Further, the low concentration impurity region is formed between the twochannel forming regions in the case of the above TFT structures (A-typeand B-type). Thus, a TFT characteristic is greatly varied when light isincident into a region between the two channel forming regions, ascompared with the present invention.

Also, a TFT structure disclosed in JP 07-22627 A (hereinafter called aC-type) is proposed. According to this TFT structure (C-type), althoughonly a high concentration impurity region is formed between two channelforming regions, an offset region is formed while a low concentrationimpurity region is not provided therein, which is greatly different fromthe present invention. According to the TFT structure of the presentinvention, low concentration impurity regions are formed between thechannel forming region and the source region and between the channelforming region and the drain region, an off current value is smallerthan that in the TFT structure (C-type), and an on current value islarger than that in C-type. In addition, d1>d2 in the TFT structure(C-type).

Also, with respect to the above TFT structure (C-type), a TFTcharacteristic is greatly varied when light is incident into the offsetregion provided between the channel forming region and the source regionor the drain region, as compared with the present invention in which thelow concentration impurity regions are provided between the channelforming region and the source region and between the channel formingregion and the drain region.

Also, according to the present invention, the interval d1 between theadjacent gate electrodes 109 is provided to be shorter than the width d2of the low concentration impurity regions 106 and 107 and light is hardto be incident into a region between the two channel forming regions ascompared with the conventional TFT structures (A-type, B-type, andC-type).

A comparison experiment conducted by the present inventors and itsexperimental result will be indicated below.

First, an amorphous silicon film is formed on a substrate with aninsulating surface and then crystallized to form a silicon film with acrystal structure. Then, a TFT using the silicon film as an active layeris manufactured and a pixel including the pixel TFT structure of thepresent invention, that is, the TFT in which only the high concentrationimpurity region located between the two channel forming region (23 μm×23μm) is produced. With respect to widths of respective portions in achannel direction, the widths of the gate electrode and the channelforming region are respectively set to be 2 μm and the width d2 of theLDD regions is set to be 1.3 m. Then, respective pixel TFTs in which theinterval d1 between the adjacent gate electrodes is set to 1 μm and 2 μmare manufactured and results obtained by measuring on current values andoff current values in the pixel TFTs are indicated in FIGS. 3 and 4.

Also, for comparison, a pixel including the TFT with the above A-type,that is, a pixel including the TFT in which the LDD regions and the highconcentration impurity region sandwiched by the LDD regions are locatedbetween the two channel forming regions is produced. With respect towidths of respective portions in the channel direction, the widths ofthe gate electrode and the channel forming region are respectively setto be 2 μm and the width d2 of the LDD regions is set to be 1.3 μm.Then, a pixel TFT in which the interval d1 between the adjacent gateelectrodes is set to 3 μm (LDD regions: 1 μm×2 and high concentrationimpurity region: 1 μm) is manufactured and results obtained by measuringon current values and off current values in the TFTs are similarlyindicated in FIGS. 3 and 4.

Also, for comparison, a pixel including the TFT with the above B-type,that is, a pixel including the TFT in which only the low concentrationimpurity region is located between the two channel forming regions isproduced. With respect to widths of respective portions in the channeldirection, the widths of the gate electrode and the channel formingregion are respectively set to be 2 μm and the width d2 of the LDDregions is set to be 1.3 μm. Then, respective pixel TFTs in which theinterval d1 between the adjacent gate electrodes is set to 1 μm and 2 μmare manufactured and results obtained by measuring on current values andoff current values in the TFTs are indicated in FIGS. 3 and 4.

Also, occurrence ratios of off current anomaly in the respective TFTsare obtained. With respect to a sample in which 12×17 pixels are locatedin matrix, a ratio of the number of pixels in which an off currentexceeds 100 fA is obtained as an occurrence ratio of a pixel with anabnormal off current value. As a result, 1.9% is obtained in the presentinvention, 2.7% is obtained in the A-type, and 23% is obtained in theC-type. Thus, the lowest occurrence ratio of off current anomaly isobtained in the TFT structure of the present invention. In other words,according to the TFT structure of the present invention, the occurrenceratio of off current anomaly of the TFT can be reduced to lead to theimprovement of a yield.

It is very useful to apply the TFT structure of the present invention,which is capable of suppressing a deterioration of the TFTcharacteristic by incidence light into a TFT due to various factors(natural light, multiple reflection, diffraction light, light from alight source, return light, and the like), to a pixel TFT and a TFT of adriver portion which are mounted in a liquid crystal display module. Inaddition, from the similar reason, it is also very useful to use the TFTstructure of the present invention for a light emitting display deviceincluding an EL (electro-luminescence) element and a contact type imagesensor.

Also, although the case of using the substrate with the insulatingsurface is described, a semiconductor substrate can be used.

Embodiment Mode 2

Although the example in which d1<d2 is set is indicated in EmbodimentMode 1, one example in the case where Embodiment Mode 2 of the presentinvention in which d1=d2 is set is applied to a TFT with a double gatestructure is shown in FIGS. 2A and 2B and described below.

In FIGS. 2A and 2B, reference numeral 200 denotes a substrate, 201 and202 denote channel forming regions, 203 and 205 denote a source regionand a drain region, 204 denotes a high concentration impurity region,206 and 207 denote low concentration impurity regions (LDD regions), 208denotes a gate insulating film, 209 denotes gate electrodes, 210 denotesan interlayer insulating film, and 211 and 212 denote a source electrodeand a drain electrode. Note that FIG. 2A is a cross sectional view takenalong a dotted line A-A′ of FIG. 2B which is a top view of a TFT.

The present invention is characterized in that only the highconcentration impurity region 204 is formed as a region sandwiched bythe two channel forming regions 201 and 202. An interval d1 between theadjacent gate electrodes 209, that is, a width of the high concentrationimpurity region in a channel length direction is designed to be the samelength as a width d2 of the low concentration impurity regions 206 and207. Thus, the interval between the two channel forming regions can beshortened and an area occupied by the TFT in one pixel can be reduced.In addition, since the region sandwiched by the two channel formingregions is the high concentration impurity region, light sensitivity inthe case where light is incident into a TFT for some reason is reducedwhile the resistance of the entire semiconductor layer of the TFT whichis in an on state is reduced.

Embodiment Mode 3

This embodiment mode is indicated in FIG. 21. A first light shieldinglayer 1102 is formed to correspond to a channel forming region of asemiconductor layer 1105 on a substrate 1101. The first light shieldinglayer 1102 is formed of a non-translucent material with a heatresistance such as W, Ta, Ti, or silicide thereof. The non-translucentmaterial is selected to keep stability with respect to a thermaltreatment step at 500° C. or higher which is performed for thesemiconductor layer and the like as a later step. A first insulatinglayer is formed from a silicon oxynitride film 1103 and a silicon oxidefilm 1104. The surface of the silicon oxide film may be leveled bychemical mechanical polishing (CMP).

The semiconductor layer 1105 is formed from a polycrystallinesemiconductor layer obtained by crystallizing an amorphous semiconductorfilm using thermal treatment and have a thickness of about 30 nm to 750nm. A second insulating film 1106 is formed from a silicon oxide filmwith a thickness of 30 nm to 100 nm on the semiconductor layer 1105, andthinned in a capacitor element. A gate electrode 1107 and a capacitorwiring 1108 are formed from the same layer and a third insulating layer1109 of a silicon oxide film with a thickness of 150 nm to 200 nm isformed thereon.

Second light shielding layers 1110 and 1111 are also used as electrodesfor forming contact with the source and the drain. In particular, thesecond light shielding layer 1110 is formed over the capacitor wiring1108 and composes the capacitor element. The second light shieldinglayers 1110 and 1111 are extended over the gate electrode 1107 and alsoserves as light shielding layers. In this case, when the thickness ofthe third insulating layer 1109 is set to be 150 nm to 200 nm, theamount of incidence light into the semiconductor layer 1105 is reducedeven though diffraction light is rounded. Further, there is an effectthat a capacitance of the capacitor element is increased.

A channel forming region 1120, source and drain regions 1121 and 1122,and LDD regions 1124 are formed in the semiconductor layer 1105. Asemiconductor region 1123 extended from the source region or the drainregion 1122 serves as one electrode of the capacitor element.

According to the structure shown in FIG. 21, the second light shieldinglayers 1110 and 1111 are formed over the LDD regions 1124 in which arelatively large variation in conductivity is caused by aphotoconductive effect to become light shielding layers. Thus, almostall stray light can be blocked. A fourth insulating layer 1112, sourceand drain wirings 1113 and 1114, a fifth insulating layer 1115, a thirdlight shielding layer 1116, a sixth insulating layer 1117, and a pixelelectrode 1118 are formed on the second light shielding layers 1110 and1111.

According to the structure of the present invention, stray lightincluding diffraction light can be completely blocked. However, it isconcerned that the second light shielding layers overlap immediatelyabove the LDD regions 1124 to change electric field distributions of theLDD regions 1124 and cause the influence on a characteristic of a TFT.

FIGS. 23A and 23B show a result obtained by simulating an electric fieldstrength distribution in a transverse direction of the LDD region in thestructure of the present invention which is similar to the structureshown in FIG. 21. FIG. 23A shows an element structure used forcalculation. An interval between the first light shielding layer and theLDD region is set to be 580 nm, a thickness of the gate insulating filmis set to be 80 nm, and an interval between the LDD region and thesecond light shielding layer is set to be 180 nm. A gate voltage is −8 Vand a drain voltage is +5 V. FIGS. 24A and 24B show a result obtained bya similar simulation in a conventional structure in which the secondlight shielding layer is not located immediately over the LDD region.

When FIG. 23B is compared with FIG. 24B, it is clear that an electricfield strength of the LDD portion in an end portion of the gateelectrode is increased by the influence of the electric field from thesecond light shielding layer in the case of using the structure of thepresent invention. However, when the influence is examined for aprototyped TFT, it is proved that an off current is not almost increasedas shown in FIG. 25. Thus, it is found that the light shielding propertycan be improved without deteriorating a characteristic of a TFTaccording to the structure of the present invention.

Embodiment Mode 4

FIG. 26 shows a cross sectional structure of a pixel according to thepresent invention and a structure in which a TFT and a pixel electrodeand a capacitor portion which are connected with the TFT are formed. Afirst light shielding layer 1202 is formed on a substrate 1201 tocorrespond to a channel forming region of an active layer of acrystalline semiconductor film.

The first light shielding layer 1202 is formed of a non-translucentmaterial with a heat resistance such as W, Ta, Ti, or silicide thereof.The non-translucent material is selected to keep stability with respectto a thermal treatment step at 500° C. or higher which is performed forthe semiconductor layer and the like as a later step. A first insulatinglayer is formed from a silicon oxynitride film 1203 and a silicon oxidefilm 1204. The surface of the silicon oxide film may be leveled bychemical mechanical polishing (CMP).

The active layer is formed from at least two layers of polycrystallinesemiconductor films. A first crystalline semiconductor film 1205 isformed at a thickness of about 30 nm to 300 nm by crystallizing anamorphous semiconductor film using thermal treatment.

Further, an amorphous semiconductor film is formed at a thickness of 30nm to 300 nm on the first crystalline semiconductor film 1205 andcrystallized by irradiation of laser light to form a second crystallinesemiconductor film 1206. A solid laser oscillating device, a gas laseroscillating device, or a metallic laser oscillating device can beapplied as a light source for laser light. A continuous oscillationsolid laser device is most preferable. A continuous oscillation YAGlaser, a YVO₄ laser, a YLF laser, a YAlO₃ laser, a glass laser, a rubylaser, an alexandrite laser, or a Ti: sapphire laser can be applied.

Also, it is desirable that laser light is converted into harmonic by anon-linear optical element. For example, it is known that the YAG laseremits laser light with a wavelength of 1065 nm as a fundamental wave.Since an absorption coefficient of the laser light to a semiconductorfilm is low, it is difficult to crystallize only an amorphoussemiconductor film without damaging an insulating film formed as a basefilm and a substrate. When the second harmonic (532 nm), the thirdharmonic (355 nm), the fourth harmonic (266 nm), or the fifth harmonic(213 nm) is produced by a non-linear optical element without using afundamental wave and laser light with such a wavelength is irradiated,only an amorphous semiconductor film is selectively heated forcrystallization in accordance with a light absorption coefficient of asemiconductor film.

The crystalline semiconductor films formed by such two-stepcrystallization processing is a film which has a large grain size and asmall crystal defect, and has a similar characteristic to a singlecrystal in a crystal grain. When the second crystalline semiconductorfilm is formed, the first crystalline semiconductor film becomes aprotective film at laser irradiation and serves to relax an internalstress to a different kind of lower portion film. In addition, theinfluence of lattice unconformity at a connection portion between thefirst crystalline semiconductor layer and the second crystallinesemiconductor film is small. Thus, even when the active layer of the TFTis formed by laminating two layers, there is no case where the influenceis caused by the difference between layers. By selective crystallizationto form the second crystalline semiconductor film, the alternation ofthe light shielding films due to the irradiation of laser light isprevented, and diffuse reflection of the laser light reflected from thelight shielding film formed at the lower layer side of the firstcrystalline semiconductor film is prevented. Therefore, the crystallinesemiconductor films with no distortion can be formed.

A second insulating film 1207 of a silicon oxide film with a thicknessof 30 nm to 100 nm is formed on the semiconductor layer and thinned in acapacitor element. A gate electrode 1208 and a capacitor wiring 1209 areformed from the same layer and a third insulating layer 1210 of asilicon oxide film with a thickness of 150 nm to 200 nm is formedthereon.

Second light shielding layers 1211 and 1212 also serve as electrodes forforming contact with the source and the drain. In particular, the secondlight shielding layer 1211 is formed over the capacitor wiring 1209 tocomposes the capacitor element. The second light shielding layers 1211and 1212 are extended over the gate electrode 1208 to improve the lightshielding property. In this case, when the thickness of the thirdinsulating layer is set to be 150 nm to 200 nm, the amount of incidencelight into the active layer 1205 is reduced although diffraction lightis rounded. Further, there is an effect that a capacitance of thecapacitor portion is increased.

A channel forming region 1221, source and drain regions 1222 and 1223,and LDD regions 1225 are formed in the active layer. A semiconductorregion 1224 extended from the source region or the drain region 1223serves as one electrode of the capacitor element.

According to the structure shown in FIG. 26, the second light shieldinglayers 1211 and 1212 are formed over the LDD regions 1225 in which arelatively large variation in conductivity is caused by aphotoconductive effect to become light shielding layers. Thus, almostall stray light can be blocked. A fourth insulating layer 1213, sourceand drain wirings 1214 and 1215, a fifth insulating layer 1216, a thirdlight shielding layer 1217, a sixth insulating layer 1218, and a pixelelectrode 1219 are formed on the second light shielding layers 1211 and1212.

The present invention that provides the above structures is described inmore detail based on the following embodiments.

Embodiment 1

Embodiment 1 of the present invention will be described with referenceto FIGS. 5 to 8. Here a detailed description is given on a method ofsimultaneously forming on the same substrate a TFT for a pixel portionand TFTs (an n-channel TFT and a p-channel TFT) for driver circuits thatare provided in the periphery of the pixel portion.

First, a base insulating film 301 is formed on a glass substrate 300, afirst semiconductor film with crystalline structure is formed, and thesemiconductor film is etched into desired shapes to form semiconductorlayers 302 to 306 that are separated from one another like islands.

The base insulating film 301 provided on the glass substrate inEmbodiment 1 has a two-layered structure. However, the base insulatingfilm may be a single layer or three or more layers of insulating films.The first layer of the base insulating film 301 is a first siliconoxynitride film (composition ratio: Si=32%, O=27%, N=24%, H=17%) formedto have a thickness of 50 nm by plasma CVD with as reaction gas SiH₄,NH₃, and N₂O. The second layer of the base insulating film 301 is asecond silicon oxynitride film (composition ratio: Si=32%, O=59%, N=7%,H=2%) formed to have a thickness of 100 nm by plasma CVD with asreaction gas SiH₄ and N₂O.

Next, an amorphous silicon film is formed on the base insulating film301 by plasma CVD to a thickness of 50 nm. Then nickel acetate solutioncontaining 10 ppm of nickel by weight is applied by a spinner to thesemiconductor film. Instead of application, sputtering may be used tospray nickel element to the entire surface.

Next, heat treatment is performed to crystallize the amorphoussemiconductor film to obtain the semiconductor film with crystallinestructure. For this heat treatment, thermal treatment of the electricfurnace or irradiation of strong light is used. In the case of using thethermal treatment of the electric furnace, the heat treatment isperformed at 500 to 650° C. for 4 to 24 hours. The silicon film with acrystalline structure is obtained by performing the thermal treatment(550° C., four hours) for crystallization after the thermal treatment(500° C., one hour) for dehydration. In Embodiment 1, crystallization isperformed by the thermal treatment using the furnace. However,crystallization can also be performed by the thermal treatment using thelamp anneal device.

Next, the semiconductor film is irradiated with the first laser light(XeCl: wavelength, 308 nm) in an atmosphere or an oxygen atmosphere toincrease the crystallization ratio and repair defects remaining in thecrystal grains. The laser light used is excimer laser light with awavelength of 400 nm or less, or second harmonic or third harmonic ofYAG laser. In either case, pulse laser light with a repetition frequencyof about 10 to 1000 Hz is collected by an optical system into a beam of100 to 500 mJ/cm², which irradiates the surface of the silicon film byscanning at an overlap ratio of 90 to 95%. Here, the first laser lightis irradiated under conditions of a repetition frequency of 30 Hz andenergy density 476 mJ/cm². The irradiation of the first laser light atthis point is very important in order to remove or reduce a rare gaselement (Ar, here) in the film. The oxide film formed by irradiating thefirst laser light and an oxide film formed by treating the surface withozone water for 120 seconds together form a barrier layer that has athickness of 1 to 5 nm in total.

On the barrier layer, an amorphous silicon film containing argon elementas a gettering site is formed to have a thickness of 150 nm bysputtering. The conditions for forming the amorphous silicon film bysputtering in Embodiment 1 include setting the film formation pressureto 0.3 Pa, the gas (Ar) flow rate to 50 sccm, the film formation powerto 3 kW, and the substrate temperature to 150° C. The amorphous siliconfilm formed under the above conditions contains argon element at anatomic concentration of 3×10²⁰ to 6×10²⁰/cm³, and contains oxygen in anatomic concentration of 1×10¹⁹ to 3×10¹⁹/cm³. Thereafter, a lampannealing apparatus is used for thermal treatment at 650° C. for 3minutes to perform gettering.

With the barrier layer as an etching stopper, the amorphous silicon filmcontaining argon element, which is a gettering site, is selectivelyremoved. The barrier layer is then selectively removed using dilutedfluoric acid. It is desirable to remove the barrier layer that of oxidefilms after gettering since nickel tends to move into a regioncontaining oxygen at a high concentration during gettering.

The second laser light is irradiated in a nitrogen atmosphere or vacuumatmosphere to smooth the surface of the semiconductor film. Excimerlaser light with a wavelength equal to or less than 400 nm, or thesecond or the third harmonic of a YAG laser, is used for the laser light(the second laser light). In addition, light emitted from an ultravioletlight lamp may also be used as a substitute for the excimer laser light.Note that the energy density of the second laser light is made largerthan the energy density of the first laser light, preferably from 30 to60 mJ/cm² larger. Here, the second laser light is irradiated in anatmosphere with a repetition frequency of 30 Hz and energy density of537 mJ/cm². The P-V value of the unevenness on the surface of thesemiconductor film become equal to or less than 5 nm.

Although the second laser light is irradiated to the whole surface inEmbodiment 1, at least a pixel portion may also be irradiatedselectively since the reduction of off current is effective especiallyto TFTs of the pixel portion.

Next, a thin oxide film is formed by using ozone water on the surface ofthe obtained silicon film with a crystalline structure (also called apolysilicon film), and a resist mask is formed for etching to obtain thesemiconductor layers with desired shapes, separated from one anotherlike islands. After the semiconductor layers are obtained, the resistmask is removed.

In addition, in order to control the threshold (Vth) voltage of TFTs,the impurity element that gives the p-type or n-type conductivity may bedoped to the semiconductor layers after forming the semiconductorlayers. Impurity elements known to give semiconductor the p-typeconductivity are Group 13 elements in the periodic table, such as boron(B), aluminum (Al), and gallium (Ga). Impurity elements known to give asemiconductor the n-type conductivity are Group 15 elements in theperiodic table, such as phosphorus (P) and arsenic (As).

An etchant containing fluoric acid is used to remove the oxide film andwash the surface of the silicon film at the same time. Then, aninsulating film mainly containing silicon as a gate insulating film 307is formed. The gate insulating film in Embodiment 1 is a siliconoxynitride film (composition ratio: Si=32%, O=59%, N=7%, H=2%) formed byplasma CVD to have a thickness of 115 nm.

As shown in FIG. 5A, a first conductive film 308 a with a thickness of20 to 100 nm, a second conductive film 308 b with a thickness of 100 to400 nm, and a third conductive film 308 c with a thickness of 20 to 100nm are layered on the gate insulating film 307. In Embodiment 1, a 50 nmthick tungsten film, a 500 nm thick Al—Ti (alloy of aluminum andtitanium) film, and a 30 nm thick titanium film are layered on the gateinsulating film 307 in the order stated.

Conductive materials for forming the first to third conductive films areelements selected from the group consisting of Ta, W, Ti, Mo, Al, andCu, or alloy or compound materials mainly containing the above element.Alternatively, as the first to third conductive films, a polycrystallinesilicon film represented by a semiconductor film doped with an impurityelement such as phosphorus. For instance, the first conductive film maybe a tungsten nitride film instead of the tungsten film, the secondconductive film may be an Al—Si (alloy of aluminum and silicon) filminstead of the Al—Ti (alloy of aluminum and titanium) film, and thethird conductive film may be a titanium nitride film instead of thetitanium film. It is not always necessary to have three layers ofconductive films, and two layers of conductive films, a tantalum nitridefilm and a tungsten film, for example, may be employed.

As shown in FIG. 5B, resist masks 310 to 315 are formed with lightexposure to conduct the first etching treatment for forming gateelectrodes and wiring lines. The first etching treatment is conductedunder first and second etching conditions. ICP (inductively coupledplasma) etching is employed. The films can be etched into desired tapershapes by using ICP etching and adjusting etching conditions (the amountof electric power applied to a coiled electrode, the amount of electricpower applied to a substrate side electrode, the temperature of thesubstrate side electrode, etc.) suitably. Examples of etching gas usedinclude chlorine-based gas, typically, Cl₂, BCl₃, SiCl₄, or CCl₄,fluorine-based gas, typically, CF₄, SF₆, or NF₃, and O₂.

There is no limitation on selection of the etching gas, BCl₃, Cl₂, andO₂ are suitable here. The gas flow rate thereof is set to 65:10:5(unit:sccm), and RF (13.56 MHz) electric power of 450 W is given to acoiled electrode at a pressure of 1.2 Pa to generate plasma for 117second etching. The substrate side (sample stage) also receives RF(13.56 MHz) power of 300 W to apply substantially negative self-biasvoltage. Under the first etching conditions, the Al film and the Ti filmare etched and edge portions of the first conductive layer are tapered.

Switched to the second etching conditions, the etching gas is changed toCF₄, Cl₂, and O₂. The gas flow rate thereof is set to 25:25:10(unit:sccm), and RF (13.56 MHz) power of 500 W is given to a coiledelectrode at a pressure of 1 Pa to generate plasma for etching for about30 seconds. The substrate side (sample stage) also receives RF (13.56MHz) power of 20 W to apply substantially negative self-bias voltage.Under the second etching conditions with mixing CF₄ and Cl₂, the Alfilm, the Ti film, and the W film are etched to about the same degree.In order to perform etching without leaving any residue on the gateinsulating film, the etching time is prolonged by approximately 10 to20%.

In the first etching treatment, the edge portions of the firstconductive layers, second conductive layers, and third conductive layersare tapered by forming the resist masks into proper shapes and by theeffect of the bias voltage applied to the substrate. The angle of thetapered portions is 15 to 45°. First shape conductive layers 317 to 322are thus formed from the first conductive layers, the second conductivelayers, and the third conductive layers (the first conductive layers 317a to 322 a, the second conductive layers 317 b to 322 b and the thirdconductive layers 317 c to 322 c) through the first etching treatment.Denoted by 316 is a gate insulating film and regions thereof that arenot covered with the first shape conductive layers 317 to 322 are etchedand thinned by about 20 to 50 nm.

Without removing the resist masks 310 to 315, second etching treatmentis conducted next as shown in FIG. 5C. BCl₃ and Cl₂ are used as etchinggas, the gas flow rate thereof is set to 20:60 (unit:sccm), and RF(13.56 MHz) power of 600 W is given to a coiled electrode at a pressureof 1.2 Pa to generate plasma for etching. The substrate side (samplestage) also receives RF (13.56 MHz) power of 100 W. Under these thirdetching conditions, the second conductive layers and the thirdconductive layers are etched. The aluminum film containing a minuteamount of titanium and the titanium film are thus subjected toanisotropic etching under the third etching conditions to form secondshape conductive layers 324 to 329 (the first conductive layers 324 a to329 a, the second conductive layers 324 b to 329 b and the thirdconductive layers 324 c to 329 c). Denoted by 323 is a gate insulatingfilm and regions thereof that are not covered with the second shapeconductive layers 324 to 329 are etched and thinned slightly.

Without removing the resist masks, the first doping treatment isconducted to dope an impurity element that gives the n-type conductivityto the semiconductor layers. The doping treatment is performed with iondoping or ion implantation. In ion doping, the dose is set to 1.5×10¹⁴atoms/cm² and the acceleration voltage is set to 600 to 100 keV.Typically, phosphorus (P) or arsenic (As) is used as an impurity elementthat gives the n-type conductivity. In this case, the second shapeconductive layers 324 to 328 serve as masks against the impurity elementthat gives the n-type conductivity and first impurity regions 330 to 334are formed in a self-aligning manner. The first impurity regions 330 to334 contain the impurity element that gives the n-type conductivity at aconcentration of 1×10¹⁶ to 1×10¹⁷/cm³.

Although the first doping treatment is conducted without removing theresist masks in Embodiment 1, the resist mask may be removed before thefirst doping treatment.

After the resist masks are removed, resist masks 335 and 336 are formedas shown in FIG. 6A for second doping treatment. The mask 335 functionsfor protecting a channel formation region and its surrounding regions inthe semiconductor layer that forms one of n-channel TFTs of the drivercircuit, and the mask 336 functions for protecting a channel formationregion and its surrounding regions in the semiconductor layer that formsa TFT of the pixel portion.

The second doping treatment employs ion doping to dope the semiconductorlayers with phosphorus (P) with the dose to 1.5×10¹⁵ atoms/cm² and theacceleration voltage to 60 to 100 keV. Here, impurity regions are formedin the semiconductor layers utilizing the difference in thickness of thesecond shape conductive layers 324 to 328 and the gate insulating film323. The regions covered with the masks 335 and 336 are not doped withphosphorus (P). Second impurity regions 380 to 382 and third impurityregions 337 to 341 are thus formed. The third impurity regions 337 to341 are doped with an impurity element that gives the n-typeconductivity at a concentration of 1×10² to 1×10²¹/cm³. The secondimpurity regions are doped with the impurity element that gives then-type conductivity at a lower concentration than in the third impurityregions due to the difference in thickness of the gate insulating film.The concentration of the impurity element in the second impurity regionsis 1×10¹⁸ to 1×10¹⁹/cm³. Regions to become storage capacitor can becovered with masks.

In a region placed between two channel formation regions of the pixelportion, only the third impurity region is formed in the second dopingtreatment. With such a structure, the resistance of the wholesemiconductor layer in an ON state of TFT is decreased and ON currentcan be increased, and at the same time, the carrier life time by thelight excitation generated in the high impurity element region is weak,and the light sensitivity can be decreased.

After the resist masks 335 and 336 are removed, resist masks 342 to 344are newly formed as shown in FIG. 6B for the third doping treatment.Through the third doping treatment, a fourth impurity region 347 andfifth impurity regions 345 and 346 are formed in the semiconductor layerfor forming the p-channel TFT. The fourth and fifth impurity regions aredoped with an impurity element that gives the p-type conductivity. Thefourth impurity region is formed in a region that overlaps one of thesecond shape conductive layers and is doped with an impurity elementthat gives the p-type conductivity at a concentration of 1×10¹⁸ to1×10²⁰/cm³. The fifth impurity regions 345 and 346 are doped with animpurity element that gives the p-type conductivity at a concentrationof 1×10²⁰ to 1×10²¹/cm³. The fifth impurity region 346 is doped withphosphorus (P) in the previous step. However, through the third dopingtreatment, the region 346 is doped with an impurity element that givesthe p-type conductivity at 1.5 to 3 times higher concentration than theconcentration of phosphorus, and therefore has the p-type conductivity.

Fifth impurity regions 348 and 349 and a fourth impurity region 350 areformed in the semiconductor layer for forming a storage capacitor in thepixel portion.

Through the above steps, the impurity regions with the n-type or p-typeconductivity are formed in the respective semiconductor layers. Thesecond shape conductive layers 324 to 327 serve as gate electrodes. Thesecond shape conductive layer 328 serves as one of electrodesconstituting the storage capacitor in the pixel portion. The secondshape conductive layer 329 forms a source wiring line in the pixelportion.

Next, an insulating film (not shown in the drawing) is formed to coverthe surface almost completely. The insulating film in Embodiment 1 is asilicon oxide film formed by plasma CVD to have a thickness of 50 nm.The insulating film is not limited to the silicon oxide film, and asingle layer or a laminate layer of other insulating films that containssilicon may be used instead.

The next step is activation of the impurity elements doped in thesemiconductor layers. The activation step is achieved by rapid thermalannealing (RTA) using a lamp light source, irradiation from the backsidewith YAG laser or excimer laser, or heat treatment using a furnace, or acombination of these methods. Since a material mainly containingaluminum is used for the second conductive layers in Embodiment 1,heating conditions in the activation step has to be set with taking intoconsideration the heat resistance of the second conductive layers.

During the activation treatment, the gettering, nickel used as acatalyst in crystallization is simultaneously moved to the thirdimpurity regions 337, 339, and 340 and the fifth impurity regions 346and 349 that contain high concentration of phosphorus. The concentrationof nickel is reduced in the semiconductor layers for mainly formingchannel formation regions. The TFTs that have the channel formationregions with the reduced nickel concentration have a lower OFF currentvalue and provide high field effect mobility with a good crystallinity,and therefore excellent characteristics are achieved. In Embodiment 1,gettering has already been conducted once in accordance with the methodshown in Embodiment Mode 1 in forming the semiconductor layers,gettering with phosphorus at this time is the second gettering. If thefirst gettering is performed sufficiently, the second time gettering isnot particularly necessary.

Although the insulating film is formed before the activation inEmbodiment 1, the insulating film may be formed after the activation.

Next, a silicon nitride film is formed as a first interlayer insulatingfilm 351 and heat treatment (at 300 to 550° C. for 1 to 12 hours) isperformed on the first interlayer insulating film to hydrogenate thesemiconductor layers. (FIG. 6C) This step is performed for terminatingdangling bonds in the semiconductor layers using hydrogen contained inthe first interlayer insulating film 351. Irrespective of the presenceor absence of the insulating film that is a silicon oxide film (notshown), the semiconductor layers can be hydrogenated. However, heatingconditions in the hydrogenation step has to be set with taking intoconsideration the heat resistance of the second conductive layers sincea material mainly containing aluminum is used for the second conductivelayers in Embodiment 1. Other employable hydrogenation measures includeplasma hydrogenation (which uses hydrogen excited by plasma).

On the first interlayer insulating film 351, a second interlayerinsulating film 374 is formed from an organic insulating material. InEmbodiment 1, an acrylic resin film with a thickness of 1.6 μm isformed. A contact hole reaching the source wiring line 327 and contactholes reaching respective impurity regions are formed next. InEmbodiment 1, pluralities of etching processes are sequentiallyconducted. The contact holes are formed by etching the second interlayerinsulating film with the first interlayer insulating film as an etchingstopper, then etching the first interlayer insulating film with theinsulating film (not shown) as an etching stopper, and then etching theinsulating film (not shown).

Thereafter, wiring lines and a pixel electrode are formed using Al, Ti.Mo, W, or the like. It is desirable materials for the electrodes andpixel electrode are highly reflective materials such as a film mainlycontaining Al or Ag, or a laminate of a film mainly containing Al and afilm mainly containing Ag. Thus formed are source or drain wiring lines353 to 358, a gate wiring line 360, a connection wiring line 359, and apixel electrode 361.

A driver circuit that has an n-channel TFT, a p-channel TFT, and ann-channel TFT, and a pixel portion that has an n-channel TFT and astorage capacitor are formed on the same substrate by the methoddescribed above. (FIG. 7) Such a substrate is called in thisspecification as an active matrix substrate for conveniences' sake.

In FIG. 7, the pixel TFT (first n-channel TFT) in the pixel portion hasa channel formation region 371, a first impurity region 372 formedoutside of the second shape conductive layer 327 that serves as a gateelectrode, and a third impurity regions 373 and 374 that function as asource region dr a drain region. In a region 377 placed betweentwo-channel formation regions, phosphorus with the same concentration asthat in a source region or drain region is doped. The width of theregion 377 (width in the direction of channel formation region) isnarrower than that of the first impurity region (width in the directionof channel formation region) that functions as LDD regions.

A fourth impurity region 376 and a fifth impurity region 377 are formedin the semiconductor layer that functions as one of the electrodes ofthe storage capacitor. The storage capacitor is composed of the secondshape electrode 328 and the semiconductor layer 306 with an insulatingfilm (the same film as the gate insulating film) as dielectric.

In FIG. 8, an example of top view of a pixel is shown. The crosssectional view taken along the line A-A′ in FIG. 8 is corresponding tothe line A-A′ in FIG. 7. The cross sectional view taken along the lineB-B′ in FIG. 8 is corresponding to the line B-B′ in FIG. 7. The samereference numbers as FIG. 7 are used in FIG. 8.

In FIG. 7, the n-channel TFT (second n-channel TFT) of the drivercircuit has u channel formation region 362, a second impurity region 363partially overlapping the second shape conductive layer 324 that servesas a gate electrode, and a third impurity region 364 that functions as asource region or a drain region. The p-channel TFT has a channelformation region 365, a fourth impurity region 366 partially overlappingthe second shape conductive layer 325 that serves as a gate electrode,and a fifth impurity region 367 that functions as a source region or adrain region. The n-channel TFT (second n-channel TFT) has a channelformation region 368, a second impurity region 369 partially overlappingthe second shape conductive layer 326 that serves as a gate electrode,and a third impurity region 370 that functions as a source region or adrain region. The n-channel TFTs and the p-channel TFT can be used toform a shift register circuit, a buffer circuit, a level shiftercircuit, a latch circuit, and the like.

Embodiment 2

Embodiment 2 describes a process of manufacturing an active matrixliquid crystal display device from the active matrix substratefabricated in Embodiment 1. The description is given with reference toFIG. 9.

After the active matrix substrate as illustrated in FIG. 15 is obtainedin accordance with Embodiment 1, an orientation film is formed on theactive matrix substrate of FIG. 15 and subjected to rubbing treatment.In this embodiment, before the orientation film is formed, an organicresin film such as an acrylic resin film is patterned to form columnarspacers for keeping an interval between substrates in desired positions.The columnar spacers may be replaced by spherical spacers sprayed ontothe entire surface of the substrate.

An opposite substrate is prepared next. The opposite substrate has acolor filter in which colored layers and light-shielding layers arearranged with respect to the pixels. A light-shielding layer is alsoplaced in the driver circuit portion. A leveling film is formed to coverthe color filter and the light-shielding layer. On the leveling film, anopposite electrode of a transparent conductive film is formed in thepixel portion. An orientation film is formed over the entire surface ofthe opposite substrate and is subjected to rubbing treatment.

Then the opposite substrate is bonded to the active matrix substrate onwhich the pixel portion and the driver circuits are formed, with asealing member. The sealing member has filler mixed therein, and the twosubstrates are bonded with a uniform interval by the filler togetherwith the columnar spacers. Thereafter a liquid crystal material isinjected between the substrates and an encapsulant (not shown) is usedto completely seal the substrates. A known liquid crystal material canbe used. The active matrix liquid crystal display device is thuscompleted. If necessary, the active matrix substrate or the oppositesubstrate is cut into pieces with desired shapes. The display device maybe appropriately provided with a polarizing plate using a knowntechnique. Then FPCs are attached using a known technique.

The structure of the thus obtained liquid crystal module is describedwith reference to the top view in FIG. 9.

A pixel portion 804 is placed in the center of an active matrixsubstrate 801. A source signal line driver circuit 802 for drivingsource signal lines is positioned above the pixel portion 804. Gatesignal line driver circuits 803 for driving gate signal lines are placedin the left and right of the pixel portion 804. Although the gate signalline driver circuits 803 are symmetrical with respect to the pixelportion in Embodiment 2, the liquid crystal module may have only onegate signal line driver circuit on one side of the pixel portion. Adesigner can choose the arrangement that suits better considering thesubstrate size or the like of the liquid crystal module. However, thesymmetrical arrangement of the gate signal line driver circuits shown inFIG. 9 is preferred in terms such as operation reliability and drivingefficiency of the circuit.

Signals are inputted to the driver circuits from flexible printedcircuits (FPC) 805. The FPCs 805 are press-fit through an anisotropicconductive film or the like after opening contact holes in theinterlayer insulating film and resin film and forming a connectionelectrode 809 so as to reach the wiring lines arranged in given placesof the substrate 801. The connection electrode is formed of ITO in thisembodiment.

A sealing agent 807 is applied along a perimeter of the substrate in theperiphery of the driver circuits and the pixel portion. Then, anopposite substrate 806 is bonded to the substrate 801 while a spacerformed in advance on the active matrix substrate keeps the gap betweenthe two substrates constant. A liquid crystal element is injectedthrough a portion that is not coated with the scaling agent 807. Thesubstrates are then sealed by an encapsulant 808. The liquid crystalmodule is completed through the above steps.

Although all of the driver circuits are formed on the substrate here,several ICs may be used for some of the driver circuits.

This embodiment can be freely combined with Embodiment Modes 1 to 4 andEmbodiment 1.

Embodiment 3

In this embodiment, an example of manufacturing a light emitting displaydevice having an electro luminescence (EL) element is described.

A pixel portion, a source driver circuit, and a gate driver circuit areformed on a substrate (e.g., a glass substrate, a crystalline glasssubstrate or a plastic substrate) having an insulating surface. Thepixel portion and the driver circuits can be obtained by a process inaccordance with one of Embodiment Mode 1. The pixel portion and thedriver circuit portions are covered with a layer of the sealing materialand the sealing material is covered with the protective film. Further,the pixel portion and the driver circuit portions are enclosed between acovering member by using an adhesive. It is desirable that the coveringmember be formed from the same material as that of the substrate, forexample, glass in order to resist deformation due to heat, externalforce, etc. The covering member formed from such a material is workedinto a recessed shape (having a depth of 3 to 10 μm) by sandblasting orthe like. It is desirable to also form a recess (having a depth of 50 to200 μm) capable of accommodating a desiccant. If a plurality of the ELmodules are manufactured on one substrate, the substrate and thecovering member, after being bonded to each other, are cut by a CO₂laser or the like so as to have the same cut end surfaces.

The structure of this embodiment as seen in the sectional view will nextbe described. An insulating film is provided on the substrate, and thepixel portion and the gate driver circuit are formed on the insulatingfilm. The pixel portion is constituted by current control TFTs and aplurality of pixels including pixel electrodes electrically connected tothe drains of the current control TFTs. The gate driver circuit isformed by using a CMOS circuit including a combination of an n-channelTFT and a p-channel TFT. TFTs circuits may be manufactured in accordancewith any of Embodiment 1.

Each pixel electrode functions as an anode of an EL element. Banks areformed at the opposite ends of the pixel electrode. An EL layer and acathode of the EL element are formed on the pixel electrode.

The EL layer (layer for emitting light and for moving carriers to emitlight) may be formed by freely combining a light emitting layer, acharge transport layer or a charge injection layer, etc. For example, alow-molecular-weight organic EL material or a high-molecular-weightorganic EL material may be used. As the EL layer, a thin film formedfrom a light emitting material (singlet compound) capable of emittinglight (fluorescence) by singlet excitation or a thin film formed from alight emitting material (triplet compound) capable of emitting light(phosphorescence) by triplet excitation may be used. An organic materialsuch as silicon carbide can be used as a charge transport layer orcharge injection layer. The organic EL material and inorganic materialfor the above-described use may be selected from various well-knownmaterials.

The cathode also functions as a wiring connected in common to all thepixels. The cathode is electrically connected to the FPC via connectionwiring. All the devices contained in the pixel portion and the gatedriver circuit are covered with the cathode, the sealing material andthe protective film.

Preferably, a material having the highest possible transparency ortranslucence for visible light is used as the sealing material. Inaddition, preferably, the sealing material has the highest possibleeffect of limiting permeation of water and oxygen.

It is also preferable to provide the protective film formed of a DLCfilm or the like at least on the surface of the sealing material(exposed surface), after the light-emitting element has been completelycovered with the sealing material. The protective film may be providedon the entire surface including the back surface of the substrate. Insuch a case, care must be exercised to avoid forming the protective filmon the region where external input terminal (FPC) is provided. To avoidfilm forming on the external input terminal region, a mask may be usedor the terminal region may be covered with a tape such as a Teflon tapeused as a masking tape in CVD apparatus.

The EL element is enclosed in the above-described structure with thesealing material and the protective film to completely isolate the ELelement from the outside and to prevent substances which promotedegradation of the EL layer by oxidation, e.g., water and oxygen fromentering the EL layer from the outside. Thus, the light-emitting devicehaving improved reliability can be obtained.

Another construction may be formed in such a manner that the pixelelectrode is used as a cathode and an anode is formed on the EL layer,light being emitted in a direction opposite to the emission direction.

This embodiment can be combined with one of Embodiment 1, EmbodimentMode 1 or Embodiment Mode 2.

Embodiment 4

A fabrication process of another top gate TFT, specifically, an activematrix substrate equipped with the top gate TFT including a lightshielding layer by providing a gate wiring at the bottom of thesemiconductor film explained. FIGS. 10A to 15B showing a top view of apart of the pixel portion and its sectional view are referred.

First, a conductive film is formed on a substrate 401 having aninsulating surface and is patterned to form scanning lines 402 (FIG.10A).

The scanning line 402 functions also as a light shielding layer forprotecting an active layer that is to be later formed from light. Thesubstrate 401 uses a quartz substrate. The scanning line 402 uses alaminate structure of a poly-silicon film (50 nm thick) and a tungstensilicide (W—Si) film (100 nm thick). The poly-Si film protectscontamination of the substrate from tungsten silicide. Besides thequartz substrate, the substrate 401 may use a glass substrate or aplastic substrate. When the glass substrate is used, it may beheat-treated in advance at a temperature lower by about 10 to about 20°C. than a glass distortion point. An underlying layer formed from aninsulating film such as a silicon oxide film, a silicon nitride film ora silicon oxynitride film is preferably formed on the surface of thesubstrate 401 on which TFT is formed, to prevent diffusion of impuritiesfrom the substrate 401. The scanning line 402 can use poly-Si doped withan impurity element for imparting a conductivity type or a conductivematerial such as WSi_(x) (x=2.0 to 2.8), Al, Ta, W, Cr or Mo, or theirlaminate structure.

Next, insulating films 403 a and 403 b for covering the scanning lines402 are formed to a thickness of 100 to 1000 nm (typically 300 to 500nm) (FIG. 10B). Here, a silicon oxide film formed to a thickness of 100nm by CVD and a silicon oxide film formed to a thickness of 280 nm byLPCVD are laminated.

After the insulating film 403 b is formed, the surface of the insulatingfilm may be chemically and mechanically polished (typically by CMP) andmade flat. For example, the surface is leveled so that its maximumheight (Rmax) is not greater than 0.5 μm, preferably not greater than0.3 μm.

Next, an amorphous semiconductor film is formed to a film thickness of10 to 100 nm. Here, the LPCVD process is used to form a 69 nm-thickamorphous silicon film. The technology disclosed in Japanese PatentLaid-Open No. 8-78329 is used to crystallize this amorphoussemiconductor film. The reference discloses the technology that a metalelement for promoting crystallization is selectively added to theamorphous silicon film and a crystalline silicon film is formed withexpanding the addition region of the metal element as the starting pointby heat-treatment. Nickel is used as the metal element for promotingcrystallization. After heat-treatment (at 450° C. for one hour) iscarried out for dehydrogenation, heat-treatment (at 600° C. for 12hours) is conducted for crystallization. Next, a laser beam (XeCl:wavelength 308 nm) is irradiated to improve a crystallization ratio andto repair defects that are left inside crystal grains. An excimer laserbeam having a wavelength of up to 400 nm or the second or third harmonicof YAG laser is used as the laser beam. In any case, a pulse laser beamhaving a repetition frequency of about 10 to about 1000 Hz is used, iscondensed to 100 to 400 mJ/cm² by using an optical system, is irradiatedwith an overlap ratio of 90 to 95% to be scanned on the silicon filmsurface.

Next, Ni is gettered from a region that is to function as the activelayer of TFT. This embodiment represents an example that uses asemiconductor film containing a rare gas element as the getteringmethod. In addition to the oxide film formed by irradiating the laserbeam as described above, the film surface is then treated with ozonewater for 120 seconds to form a barrier layer made of an oxide filmhaving a total thickness of 1 to 5 nm. An amorphous silicon filmcontaining an argon element as a gettering site is formed to a thicknessof 150 nm on the barrier layer by a sputtering process. In the filmformation condition of the sputtering process in this embodiment, a filmformation pressure is 0.3 Pa, a gas (Ar) flow rate is 50 (sccm), filmformation power is 3 kW, and a substrate temperature is 150° C. Theatomic concentration of the argon element contained in the amorphoussilicon film under the above condition is 3×10²⁰/cm³ to 6×10²⁰/cm³ andthe atomic concentration of oxygen is 1×10¹⁹/cm³ to 3×10¹⁹/cm³.Heat-treatment is then carried out at 650° C. for 3 minutes by using alamp annealing apparatus for gettering. An electric furnace may be usedin place of the lamp annealing apparatus.

The amorphous silicon film containing the argon element as the getteringsite is selectively removed by using the barrier layer as an etchingstopper. Thereafter, the barrier layer is selectively removed by usingdilute hydrofluoric acid. Since nickel is likely to migrate to a regionhaving a high oxygen concentration during gettering, it is preferred toremove the barrier layer made of the oxide film after gettering.

Next, a thin oxide film is formed on the surface of the resultingsilicon film having the crystalline structure (also called the“poly-silicon film”) by using ozone water and a resist mask is formedthereon. The silicon film is etched to obtain a desired shape, and thusa semiconductor layer 404 isolated in an island shape is formed. Theresist mask is removed after the semiconductor layer 404 is formed (FIG.10C). FIG. 10D is a top view of the pixel after the semiconductor layer404 is formed. A sectional view taken along a dotted line A-A′ in FIG.10D corresponds to FIG. 10C.

After the semiconductor layer is formed, an impurity element forimparting a p-type or an n-type may be added to control a thresholdvalue (Vth) of TFT. The elements of the Group XIII of the Periodic Tablesuch as boron (B), aluminum (Al) and gallium (Ga) are known as theimpurity elements that impart the p-type to the semiconductor. Theelements belonging to the Group XV of the Periodic Table typified byphosphorus (P) and arsenic (As) are known as the impurity elements thatimpart the n-type to the semiconductor.

Next, to form the storage capacitor, a mask 405 is formed and phosphorusis doped into a part of the semiconductor layer (region to function asthe storage capacitor) 406 (FIG. 11A).

After the mask 405 is removed, an insulating film is formed in such amanner as to cover the semiconductor layer. A mask 407 is then formed,and the insulating film on the region 406 to function as the storagecapacitor is removed (FIG. 11B).

Next, the mask 407 is removed and thermal oxidation is carried out toform an insulating film (gate insulating film) 408 a. Due to thisthermal oxidation, the final film thickness of the gate insulating filmbecomes 80 nm. Incidentally, an insulating film 408 b thinner than theother regions is formed on the region to function as the storagecapacitor (FIG. 11C). FIG. 11D is a top view of the pixel at this stage.A sectional view taken along a dotted line B-B′ in FIG. 11D correspondsto FIG. 11C.

Next, a channel dope step of adding a p-type or n-type impurity elementin a low concentration to a region to function as a channel region ofTFT is conducted either to the entire surface or selectively. Thischannel dope step is the one that controls the threshold voltage of TFT.Here, boron is doped by an ion dope method of plasma excitation ofdiborane (B₂H₆) without mass isolation. Needless to say, an ionimplantation process with mass isolation may be carried out, too.

A mask 409 is formed on the insulating film 408 a and the insulatingfilms 403 a and 403 b, and contact holes are formed in such a manner asto reach the scanning lines 402 (FIG. 12A). The mask is removed afterthe contact holes are formed.

A conductive film is formed and is then patterned to give gateelectrodes 410 and a capacitance wire 411 (FIG. 12B). This embodimentuses a laminate structure of a silicon film (150 nm thick) doped withphosphorus and tungsten silicide (150 nm thick) as the gate electrodes410 and the capacitance wire 411. In this embodiment, a double gatestructure is formed, and the space between adjacent gate electrodes (d1)is 1 μm. The storage capacitor composed of the capacitance wire 411 anda part of the semiconductor layer 406 by using the insulating film 408 bas the dielectric.

Next, phosphorus is doped in a low concentration and in self-alignmentwith the gate electrode 410 and the capacitance wire 411 as the mask(FIG. 12C). FIG. 12D shows a top view of the pixel at this stage. InFIG. 12D, the sectional view taken along a dotted line C1-C1′ and thesectional view taken along the line C2-C2′ correspond to FIG. 12C. Thephosphorus concentration doped in a low concentration is regulated to1×10¹⁶ to 5×10¹⁸ atoms/cm³, typically 3×10¹⁷ to 3×10¹⁸ atoms/cm³.

A mask 412 is then formed and phosphorus is doped in a highconcentration to form a high concentration impurity region 413 that isto function as a source region or a drain region (FIG. 13A). Thephosphorus concentration in the high concentration impurity region isregulated to 1×10²⁰ to 1×10²¹ atoms/cm³ (typically 2×10²⁰ to 5×10²⁰atoms/cm³). Incidentally, a region of the semiconductor layer 404overlapping with the gate electrode 410 is a channel formation region414 and a region of the semiconductor layer 404 covered with the mask412 is a low concentration impurity region 415 that is to function as anLDD region. In TFT of the pixel portion of this embodiment, mask 412 isnot provided between adjacent gate electrodes and only highconcentration impurity region (width 1 μm in the direction of the lengthof the channel formation) is formed between two channel formationregions in a self-alignment. The width d2 of the low impurity region isformed to 1.3 to 1.5 μm with the mask 412, and the interval (d1) of theadjacent gate electrodes is 1 μm. However, d1 and d2 are not limited tothese values provided that d1<d2. TFT of the pixel portion and TFT ofthe driver circuit are formed on the same substrate in this embodiment.TFT of the driver circuit may be provided the low impurity region onboth sides, and also the low impurity region on one side. Furthermore,the TFTs may not be provided the low impurity region on both sides.Examiners may appropriately design masks. After the impurity element isdoped, the mask 412 is removed.

To form p-channel TFT used for a driver circuit formed over the samesubstrate as the pixels, a mask covers a region to function as n-channelTFT and boron is doped to form the source or drain region, though notshown in the drawing.

After the mask 412 is removed, a passivation film 416 is formed in sucha manner as to cover the gate electrodes 410 and the capacitance wire411. Here, a silicon oxide film is formed to a thickness of 70 nm.Heat-treatment is then carried out to activate the n-type or p-typeimpurity element doped in a respective concentration to thesemiconductor layer. Here, heat-treatment is carried out at 850° C. for30 minutes.

Next, an interlayer insulating film 417 made of an organic resinmaterial is formed. This embodiment uses a 400 nm-thick acrylic resinfilm. After contact holes reaching the semiconductor layer are formed,the drain electrode 418 and the source line 419 are formed. In thisembodiment, the drain electrode 418 and the source line 419 are madefrom a three-layered laminate film that a 100 nm-thick Ti film, a 300nm-thick Ti-containing aluminum film and a 150 nm-thick Ti film arecontinuously formed by a sputtering process (FIG. 13B). The source line419 and the drain electrode 418 cut off the light to the semiconductorlayer as shown in FIG. 13B. The source line 419 and the drain electrode418 cut off light diffracted at an end part of the light shielding layerthat is to be later formed. Incidentally, the sectional view taken alonga dotted line D-D′ in FIG. 13C corresponds to FIG. 13B.

After hydrogenation treatment is conducted, an interlayer insulatingfilm 420 made of an acrylic resin is formed. Next, a conductive filmwith a light shielding property is formed at a thickness of 100 nm onthe interlayer insulating film 420 to form a light shielding layer 421(FIG. 14A). The sectional view taken along a dotted line E-E′ in FIG.14B corresponds to FIG. 14A.

Next, an interlayer insulating film 422 is formed. Contact holes arethen so formed as to reach the drain electrode 418. After a 100 nm-thicktransparent conductive film (here, an indium oxide tin (ITO) film) isformed, it is patterned to form pixel electrodes 423 and 424 (FIG. 15A).The sectional view taken along a dotted lines F-F′ in FIG. 15Bcorresponds to FIG. 15A.

In this way, the pixel TFT comprising the n-channel TFT is formed in thepixel portion while the area (aperture ratio 74.5%) of the displayregion (pixel size of 23 μm×23 μm) is secured, and a sufficient storagecapacitor (55.2 fF) can be acquired.

Therefore, the n-channel TFT having a double gate structure, the pixelportion having a storage capacitor and the driver circuit having an-channel TFT and p-channel TFT can be formed on the same substrate. Inthis specification, such substrate is referred to as an active matrixsubstrate in convenience′ sake.

Further, OFF current of the obtained pixel TFT is so small that it issuitable for TFT of the pixel portion. The fluctuation becomes smallerof the TFT characteristics.

This embodiment represents one example, and the process steps of thisembodiment are not naturally restrictive. For example, each conductivefilm can be made from an element selected from the group consisting oftantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium(Cr) and silicon (Si), or an alloy film formed of the combination ofthese elements (typically, Mo—W alloy and Mo—Ta alloy). Each insulatingfilm can use a silicon oxide film, a silicon nitride film, a siliconoxynitride film and organic resin materials (polyimide, acryl,polyamide, polyimideamide and BCB (benzocyclobutene)).

A manufacturing step of the active matrix substrate for a transparentdisplay device by using a transparent conductive film to the pixelelectrode is shown in this embodiment. However, the active matrixsubstrate for reflection display device may be formed by using materialshaving a reflection.

This embodiment can be combined with any of Embodiment Modes 1 to 4 andEmbodiment 2.

Embodiment 5

The example in which the high concentration impurity region and thesource region (or the drain region) have the same impurity concentrationis indicated in the above Embodiment Mode 1 or the above Embodiment Mode2. In this embodiment, an example in which the high concentrationimpurity region and the source region (or the drain region) havedifferent concentrations is indicated in FIGS. 16 and 17.

In FIG. 16, reference numeral 500 denotes a substrate, 501 and 502denote channel forming regions, 503 and 505 denote a source region and adrain region, 504 denotes a high concentration impurity region, 506 and507 denote low concentration impurity regions (LDD regions), 508 denotesa gate insulating film, 509 denotes gate electrodes, 510 denotes aninterlayer insulating film, and 511 and 512 denote a source electrodeand a drain electrode.

In this embodiment, one more doping step is added and a concentration ofan impurity included in the high concentration impurity region 504 ishigher than that in one of the source region and the drain region 503and 505. Since the region 504 sandwiched by the two channel formingregions has a higher concentration than one of the source region and thedrain region 503 and 505, light sensitivity is reduced in the case ofincidence light into a TFT for some reason while the resistance of theentire semiconductor layer of the TFT which is in an on state isreduced.

Note that, as in Embodiment Mode 1, only the high concentration impurityregion 504 is formed as the region sandwiched by the two channel formingregions 501 and 502. In addition, as in Embodiment Mode 1, the intervald1 between the adjacent gate electrodes 509, that is, a width of thehigh concentration impurity region in a channel length direction isdesigned to be shorter than the width d2 of the low concentrationimpurity regions 506 and 507. Thus, the interval between the two channelforming regions can be shortened and an area occupied by the TFT in onepixel can be reduced.

Also, even when the interval d1 between the adjacent gate electrodes,that is, the width of the high concentration impurity region in achannel length direction is designed to be equal to the width d2 of thelow concentration impurity regions in the TFT structure shown in FIG.16, as in Embodiment Mode 2, an effect is obtained.

In FIG. 17, reference numeral 600 denotes a substrate, 601 and 602denote channel forming regions, 603 and 605 denote a source region and adrain region, 604 denotes a high concentration impurity region, 606 and607 denote low concentration impurity regions (LDD regions), 608 denotesa gate insulating film, 609 denotes gate electrodes, 610 denotes aninterlayer insulating film, and 611 and 612 denote a source electrodeand a drain electrode.

In this embodiment, one more doping step is added and a concentration ofan impurity included in the high concentration impurity region 604 ishigher than that in low concentration impurity regions 606 and 607 andlower than that in one of the source region and the drain region 603 and605.

Note that, as in Embodiment Mode 1, only the high concentration impurityregion 604 is formed as the region sandwiched by the two channel formingregions 601 and 602. In addition, as in Embodiment Mode 1, the intervald1 between the adjacent gate electrodes 609, that is, the width of thehigh concentration impurity region in a channel length direction isdesigned to be shorter than the width d2 of the low concentrationimpurity regions 606 and 607. Thus, the interval between the two channelforming regions can be shortened and an area occupied by the TFT in onepixel can be reduced.

Also, even when the interval d1 between the adjacent gate electrodes,that is, the width of the high concentration impurity region in thechannel length direction is designed to be equal to the width d2 of thelow concentration impurity regions in the TFT structure shown in FIG.17, as in Embodiment Mode 2, an effect is obtained.

Note that this embodiment can be freely combined with any one ofEmbodiment Modes 1 to 4 and Embodiments 1 to 4. However, it is necessaryto further add a doping step of adding an impurity element to a regionbetween the two channel forming regions in the case of combining.

Embodiment 6

The TFT fabricated by implementing the present invention can be utilizedfor various modules (active matrix liquid crystal module, active matrixEL module and active matrix EC module). Namely, all of the electronicapparatuses are completed by implementing the present invention.

Following can be given as such electronic apparatuses: video cameras;digital cameras; head mounted displays (goggle type displays); carnavigation systems; projectors; car stereo; personal computers; portableinformation terminals (mobile computers, mobile phones or electronicbooks etc.) etc. Embodiments of these are shown in FIGS. 18A to 18F, 19Ato 19D and 20A to 20C.

FIG. 18A is a personal computer which comprises: a main body 2001; animage input section 2002; a display section 2003; and a keyboard 2004.The present invention can be applied to the display section 2003.

FIG. 18B is a video camera which comprises: a main body 2101; a displaysection 2102; a voice input section 2103; operation switches 2104; abattery 2105 and an image receiving section 2106. The present inventioncan be applied to the display section 2102.

FIG. 18C is a mobile computer which comprises: a main body 2201; acamera section 2202; an image receiving section 2203; operation switches2204 and a display section 2205. The present invention can be applied tothe display section 2205.

FIG. 18D is a goggle type display, which comprises: a main body 2301; adisplay section 2302; and an arm section 2303. The present invention canbe applied to the display section 2302.

FIG. 18E is a player using a recording medium which records a program(hereinafter referred to as a recording medium) which comprises: a mainbody 2401: a display section 2402; a speaker section 2403; a recordingmedium 2404; and operation switches 2405. This apparatus uses DVD(digital versatile disc), CD, etc. for the recording medium, and canperform music appreciation, film appreciation, games and use forInternet. The present invention can be applied to the display section2402.

FIG. 18F is a digital camera which comprises: a main body 2501; adisplay section 2502; a view finder 2503; operation switches 2504; andan image receiving section (not shown in the figure). The presentinvention can be applied to the display section 2502.

FIG. 19A is a front type projector, which comprises: a projection system2601; and a screen 2602. The present invention can be applied to theliquid crystal module 2808, which forms a part of the projection system2601 to complete the whole system.

FIG. 19B is a rear type projector, which comprises: a main body 2701; aprojection system 2702; a mirror 2703; and a screen 2704. The presentinvention can be applied to the liquid crystal module 2808, which formsa part of the projection system 2702 to complete the whole system.

FIG. 19C is a diagram which shows an example of the structure of aprojection system 2601 and 2702 in FIGS. 19A and 19B, respectively. Eachof projection systems 2601 and 2702 comprises: an optical light sourcesystem 2801; mirrors 2802 and 2804 to 2806; a dichroic mirror 2803; aprism 2807; a liquid crystal module 2808; a phase differentiating plate2809; and a projection optical system 2810. The projection opticalsystem 2810 comprises an optical system having a projection lens. Thoughthis embodiment shows an example of 3-plate type, this is not to limitto this example and a single plate type may be used for instance.Further, an operator may appropriately dispose an optical lens, a filmwhich has a function to polarize light, a film which adjusts a phasedifference or an IR film, etc. in the optical path shown by an arrow inFIG. 19C.

FIG. 19D is a diagram showing an example of a structure of an opticallight source system 2801 in FIG. 19C. In this embodiment, the opticallight source system 2801 comprises: a reflector 2811; a light source2812; lens arrays 2813 and 2814; a polarizer conversion element 2815;and a collimator lens 2816. Note that the optical light source systemshown in FIG. 19D is merely an example and the structure is not limitedto this embodiment. For instance, an operator may appropriately disposean optical lens, a film, which has a function to polarize light, a filmthat adjusts a phase difference or an IR film, etc.

Note that the projectors shown FIGS. 19A to 19D are the cases of using atransmission type electro-optical device, and applicable examples of areflection type electro-optical device and an EL module are not shown.

FIG. 20A is a mobile phone which comprises: a main body 2901; a voiceoutput section 2902; a voice input section 2903; a display section 2904;operation switches 2905; an antenna 2906; and an image input section(CCD, image sensor, etc.) 2907 etc. The present invention can be appliedto the display section 2904.

FIG. 20B is a portable book (electronic book) which comprises: a mainbody 3001; display sections 3002 and 3003; a recording medium 3004;operation switches 3005 and an antenna 3006 etc. The present inventioncan be applied to the display sections 3002 and 3003.

FIG. 20C is a display, which comprises: a main body 3101; a supportingsection 3102; and a display section 3103 etc. The present invention canbe applied to the display section 3103. In addition, the display shownin FIG. 20C is small and medium type of large type, for example, screenof the display sized 5 to 20 inches. Moreover, it is preferable tomass-produce to form such sized display section by executing a multiplepattern using a substrate sized 1×1 m.

As described above, the applicable range of the present invention isvery large, and the invention can be applied to electronic apparatusesof various areas. Note that the electronic devices of this embodimentcan be achieved by combining one of Embodiments Modes 1 to 4, andEmbodiments 1 to 5.

Embodiment 7

In this embodiment, an example of steps of manufacturing an activematrix substrate, which are partly different from those in Embodiment 4,is indicated. Since steps up to the middle of a process are the sameones as Embodiment 4, the detail description is omitted here forsimplification.

In accordance with Embodiment 4, an n-type or a p-type impurity elementis added to the semiconductor layer at each concentration and then thethird insulating layer which covers gate electrode and the capacitorwiring is formed. Here, a silicon oxide film is formed at a filmthickness of 70 nm. Then, thermal treatment is performed for activatingthe n-type or p-type impurity element added to the semiconductor layerat each concentration. Here, the heat treatment is performed at 850° C.for 30 minutes.

Then, second light shielding layers 1417 and 1418 are formed. The secondlight shielding layers are formed of W, Ta, or Ti at a thickness of 100nm to 150 nm. Such a degree of thickness is sufficient to obtain lightshielding property and the thickness is determined in consideration ofselectivity to a base insulating film in etching. In other words, whenthe light shielding layers are thick, overetching is required inconsideration of a margin at etching. However, in this case, since thebase insulating film is thinned in a region in which etching is rapidlyprogressed, it is not preferable. In addition, the second lightshielding layers are in contact with the high concentration impurityregions of the semiconductor layer in the opening portions formed in theinsulating film.

Next, hydrogenation processing is performed and then a fourth insulatinglayer 1419 of an organic resin material is formed. Here, an acrylicresin film with a film thickness of 400 nm is used. Next, contact holeswhich reach the second light shielding layers 1417 and 1418 are formedand then source and drain wirings 1420 and 1421 are formed. In thisembodiment, a laminate film with a three-layer structure, which isobtained by forming a Ti film (100 nm), an aluminum film including Ti(300 nm), and a Ti film (150 nm) in succession by a sputtering method,is used for these wirings.

Next, as shown in FIG. 22A, a fifth insulating layer 1422 of acrylic isformed. A conductive layer of W, Ta, Ti, or the like is formed at athickness of 100 nm on the fifth insulating layer 1422 to form a thirdlight shielding layer 1423. Further, a sixth insulating layer 1424 isformed. Next, a contact hole which reaches the drain electrode isformed. A transparent conductive film (here, indium tin oxide (ITO)film) with a thickness of 100 nm is formed and then patterned to form apixel electrode 1425. A cross sectional view taken along the dotted lineF-F′ in FIG. 22B corresponds to FIG. 22A.

Thus, in the pixel portion, while an area (aperture ratio of 74.5%) of adisplay region (pixel size of 23 μm×23 μm) is kept, the n-channel TFT isformed and a sufficient storage capacitor (55.2 fF) can be obtained.

Also, although the example, in which the active matrix substrate for thetransmission liquid crystal display device is manufactured using thetransparent conductive film for the pixel electrode, is indicated inthis embodiment, an active matrix substrate for a reflection liquidcrystal display may be manufactured device using a material film havingreflection property for the pixel electrode.

Also, this embodiment can be freely combined with any one of EmbodimentMode 1 to Embodiment Mode 4 and Embodiment 1 to Embodiment 6.

Embodiment 8

In this embodiment, manufacturing steps of forming an active matrixsubstrate in accordance with Embodiment Mode 4 is indicated.

First, as Embodiment Mode 4, the conductive film is formed on thesubstrate with an insulating surface and patterned to form the firstlight shielding layer. The first light shielding layer is patterned toalso serve as a scan line.

The first light shielding layer serves as a light shielding layer forprotecting an active layer formed later from light. Here, a quartzsubstrate is used as the substrate and a laminate structure of apolysilicon film (film thickness of 50 nm) and a tungsten silicide(W—Si) film (film thickness of 100 nm) is used for the first lightshielding layer. The polysilicon film protects the substrate from acontamination of tungsten silicide. In addition to a quartz substrate, aglass substrate or a plastic substrate can be used as the substrate.When a glass substrate is used, thermal treatment may be performed inadvance at a lower temperature than a glass distortion point by about10° C. to 20° C. In addition, in order to prevent impurity diffusionfrom the substrate, a base film of an insulating film such as a siliconoxide film, a silicon nitride film, or a silicon oxynitride film ispreferably formed on the surface of the substrate over which a TFT isformed. Polycrystalline silicon doped with an impurity element forproviding a conductivity type, a conductive material such as WSix (x=2.0to 2.8), Al, Ta, W, Cr, Mo, or the like, or a laminate structure thereofcan be used for the first light shielding film.

Next, an insulating film for covering the first light shielding layer(first insulating layer) is formed at a film thickness of 100 nm to 1000nm (typically, 300 nm to 500 nm). Here, a silicon oxide film with a filmthickness of 100 nm using a CVD method and a silicon oxide film with afilm thickness of 280 nm using an LPCVD method are laminated.

Also, after forming the insulating film, leveling may be performed byprocessing or the like with chemically and mechanically polishing aninsulating surface (typically, a CMP technique). For example, polishingis conducted in order that a maximum height in the surface of theinsulating film (Rmax) is 0.5 μm or lower, preferably, 0.3 μm or lower.

Next, a first amorphous semiconductor film is formed at a film thicknessof 10 nm to 100 nm. Here, an amorphous silicon film is formed at a filmthickness of 69 nm by using an LPCVD method. The amorphous silicon filmcan also be formed by using a sputtering method, a plasma CVD method, orthe like as another means. Next, a first crystalline semiconductor filmis formed by crystallization using a technique described in JP 08-78329A as a technique for crystallizing the first amorphous semiconductorfilm. According to this crystallization method, a metallic element forpromoting crystallization is selectively added to an amorphous siliconfilm and then thermal treatment is performed to form a crystallinesemiconductor film in which crystallization is expanded from an addedregion as a start point. Here nickel is used as the metallic element forpromoting crystallization and thermal treatment for crystallization (at600° C. for 8 hours) is performed after thermal treatment fordehydrogenation (at 450° C. for 1 hour) is performed. Of course,crystallization is not limited to the technique described in the abovedocument and known crystallization processing can be used.

Next, nickel is gettered from a region as an active layer of a TFT.Here, an example of a gettering method, in which gettering is performedusing an amorphous semiconductor film including a noble gas, isindicated. The surface is processed with ozone water for 120 seconds toform a barrier layer of the oxide film with a thickness of 1 nm to 5 nm.Then, an amorphous silicon film including an argon element is formed asa gettering cite at a film thickness of 150 nm on the barrier layer by asputtering method. With respect to a film formation condition in thesputtering method of this embodiment, a film formation pressure is setto be 0.3 Pa, a flow rate of gas (Ar) is set to be 50 (sccm), filmformation power is set to be 3 kW, and a substrate temperature is set tobe 150° C. Note that an atomic concentration of an argon elementincluded in the amorphous silicon film in the above condition is3×10²⁰/cm³ to 6×10²⁰/cm³ and an atomic concentration of oxygen is1×10¹⁹/cm³ to 3×10¹⁹/cm³. Thereafter, thermal treatment at 650° C. for 3minutes is performed for gettering with a lamp anneal apparatus. Notethat an electrical furnace may be used instead of the lamp annealapparatus.

Next, the amorphous silicon film including an argon element as thegettering cite is selectively removed using the barrier layer as anetching stopper and then the barrier layer is selectively removed usingdiluted hydrofluoric acid. Note that, it is desirable that the barrierlayer of the oxide film is removed after gettering since nickel tends toeasily move to a region with a high oxygen concentration in gettering.

Next, a second amorphous silicon film is formed at a thickness of 10 nmto 200 nm on the first crystalline semiconductor film for whichgettering processing has been completed. The second amorphous siliconfilm is crystallized by irradiation of continuous oscillating laserlight to become a second crystalline semiconductor film.

For example, when a TFT is manufactured from the first crystallinesemiconductor film, the mobility is about 300 cm²/Vs. On the other hand,when a TFT is manufactured from the second crystalline semiconductorfilm, the mobility is about 500 to 600 cm²/Vs and markedly improved.

In addition, the first crystalline semiconductor film serves as aprotective film when laser is irradiated to the second amorphous siliconfilm. Thus, there is an effect that stress to the base film is relaxed.

With respect to the active layer with a laminate structure of the firstcrystalline semiconductor film and the second crystalline semiconductorfilm, a thin oxide film is formed on the surface of the active layer byozone water, a mask of resist is formed and the active layer isprocessed by etching into a predetermined shape to form island-likeseparated active layers. After forming the island-like separated activelayers, the mask of a resist is removed.

The following steps may be conducted in accordance with Embodiment Mode4 to form TFTs, thereby completing the active matrix substrate.

Also, this embodiment can be freely combined with any one of EmbodimentMode 1 to Embodiment Mode 4 and Embodiment 1 to Embodiment 7.

Embodiment 9

In this embodiment, an example in which the first amorphoussemiconductor film is crystallized by a different method from Embodiment8 will be indicated.

In accordance with Embodiment 8, the first amorphous silicon film isformed on the base insulating film. Then, thermal treatment is performedin a nitrogen atmosphere at 600° C. for 24 hours. It may also bedirectly formed by using the LPCVD method. A crystalline semiconductorfilm formed in this embodiment has a smaller crystal grain size than thecrystalline semiconductor film formed in Embodiment 8.

Subsequently, a second amorphous silicon film is formed at a thicknessof 10 nm to 200 nm on the crystalline semiconductor film. The secondamorphous silicon film is crystallized by using continuous oscillatinglaser light to become a second crystalline semiconductor film. Thesecond crystalline semiconductor film obtained in this embodiment hasthe same characteristic as the second crystalline semiconductor filmobtained in Embodiment 8. Thus, the crystalline semiconductor filmcomposing a TFT with a superior electrical characteristic can be formed.

Also, this embodiment can be freely combined with any one of EmbodimentMode 1 to Embodiment Mode 4 and Embodiment 1 to Embodiment 7.

According to the present invention, an occupying area of a TFT in onepixel can be reduced to improve an aperture ratio of the pixel. Also,according to the present invention, a deterioration of the TFTcharacteristic by incidence light into a TFT due to various factors(natural light, multiple reflection, diffraction light, light from alight source, return light, and the like) can be suppressed. Further,according to the present invention, it can be progressed to reduce apitch of respective display pixels with increasing a definition(increasing the number of pixels) of the liquid crystal display deviceand miniaturizing the liquid crystal display device.

1. (canceled)
 2. A display device comprising: a first conductive layercomprising a first metal element; a semiconductor layer comprising afirst channel forming region and a second channel forming regionoverlapping the first conductive layer, the first channel forming regionand the second channel forming region being electrically connected inseries; a second conductive layer comprising a first gate electrode anda second gate electrode, the first gate electrode and the second gateelectrode overlapping the first channel forming region and the secondchannel forming region, respectively; and a third conductive layer and afourth conductive layer over the semiconductor layer, the thirdconductive layer being in electrical contact with one of a source regionand a drain region of the semiconductor layer, and the fourth conductivelayer being in electrical contact with the other one of the sourceregion and the drain region of the semiconductor layer, wherein thefirst channel forming region entirely overlaps with the first conductivelayer and one of the third conductive layer and the fourth conductivelayer when seen in a cross sectional view taken along a length directionof the first channel forming region.
 3. A display device comprising: afirst conductive layer comprising a first metal element; a semiconductorlayer comprising a first channel forming region and a second channelforming region overlapping the first conductive layer, the first channelforming region and the second channel forming region being electricallyconnected in series; a second conductive layer comprising a first gateelectrode and a second gate electrode, the first gate electrode and thesecond gate electrode overlapping the first channel forming region andthe second channel forming region, respectively; and a third conductivelayer and a fourth conductive layer over the semiconductor layer, thethird conductive layer being in electrical contact with one of a sourceregion and a drain region of the semiconductor layer, and the fourthconductive layer being in electrical contact with the other one of thesource region and the drain region of the semiconductor layer, whereinthe first channel forming region entirely overlaps with the firstconductive layer and one of the third conductive layer and the fourthconductive layer when seen in a cross sectional view taken along alength direction of the first channel forming region, and wherein thesecond channel forming region entirely overlaps with the firstconductive layer and the other one of the third conductive layer and thefourth conductive layer when seen in a cross sectional view taken alonga length direction of the second channel forming region.
 4. The displaydevice according to claim 3, wherein the second channel forming regionis entirely overlapped by the other one of the third conductive layerand the fourth conductive layer.
 5. A display device comprising: a firstconductive layer comprising a first metal element; a semiconductor layercomprising a first channel forming region and a second channel formingregion overlapping the first conductive layer, the first channel formingregion and the second channel forming region being electricallyconnected in series; a second conductive layer comprising a first gateelectrode and a second gate electrode, the first gate electrode and thesecond gate electrode overlapping the first channel forming region andthe second channel forming region, respectively; and a third conductivelayer and a fourth conductive layer over the semiconductor layer, thethird conductive layer being in electrical contact with one of a sourceregion and a drain region of the semiconductor layer, and the fourthconductive layer being in electrical contact with the other one of thesource region and the drain region of the semiconductor layer, whereinthe first channel forming region entirely overlaps with the firstconductive layer and one of the third conductive layer and the fourthconductive layer when seen in a cross sectional view taken along alength direction of the first channel forming region, wherein the secondchannel forming region entirely overlaps with the first conductive layerwhen seen in a cross sectional view taken along a length direction ofthe second channel forming region, and wherein the second channelforming region does not overlap with the other one of the thirdconductive layer and the fourth conductive layer.
 6. A display devicecomprising: a semiconductor layer comprising a first channel formingregion and a second channel forming region, the first channel formingregion and the second channel forming region being electricallyconnected in series; a second conductive layer comprising a first gateelectrode and a second gate electrode, the first gate electrode and thesecond gate electrode overlapping the first channel forming region andthe second channel forming region, respectively; and a third conductivelayer and a fourth conductive layer over the semiconductor layer, thethird conductive layer being in electrical contact with one of a sourceregion and a drain region of the semiconductor layer, and the fourthconductive layer being in electrical contact with the other one of thesource region and the drain region of the semiconductor layer, whereinthe first channel forming region entirely overlaps with one of the thirdconductive layer and the fourth conductive layer when seen in a crosssectional view taken along a length direction of the first channelforming region.
 7. The display device according to claim 2, wherein thefirst conductive layer and the second conductive layer are electricallyconnected to each other.
 8. The display device according to claim 3,wherein the first conductive layer and the second conductive layer areelectrically connected to each other.
 9. The display device according toclaim 5, wherein the first conductive layer and the second conductivelayer are electrically connected to each other.
 10. The display deviceaccording to claim 2, wherein the first conductive layer is continuouslyformed.
 11. The display device according to claim 3, wherein the firstconductive layer is continuously formed.
 12. The display deviceaccording to claim 5, wherein the first conductive layer is continuouslyformed.
 13. The display device according to claim 2, wherein the firstchannel forming region is entirely overlapped by the one of the thirdconductive layer and the fourth conductive layer.
 14. The display deviceaccording to claim 3, wherein the first channel forming region isentirely overlapped by the one of the third conductive layer and thefourth conductive layer.
 15. The display device according to claim 5,wherein the first channel forming region is entirely overlapped by theone of the third conductive layer and the fourth conductive layer. 16.The display device according to claim 6, wherein the first channelforming region is entirely overlapped by the one of the third conductivelayer and the fourth conductive layer.
 17. The display device accordingto claim 2, wherein any one of the first conductive layer, the secondconductive layer, and the third conductive layer has a function of alight shielding layer.
 18. The display device according to claim 3,wherein any one of the first conductive layer, the second conductivelayer, and the third conductive layer has a function of a lightshielding layer.
 19. The display device according to claim 5, whereinany one of the first conductive layer, the second conductive layer, andthe third conductive layer has a function of a light shielding layer.